1 /* 2 * Copyright (C) 2007, 2008, 2009 Free Software Foundation, Inc. 3 * 4 * This file is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 3, or (at your option) any 7 * later version. 8 * 9 * This file is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * General Public License for more details. 13 * 14 * Under Section 7 of GPL version 3, you are granted additional 15 * permissions described in the GCC Runtime Library Exception, version 16 * 3.1, as published by the Free Software Foundation. 17 * 18 * You should have received a copy of the GNU General Public License and 19 * a copy of the GCC Runtime Library Exception along with this program; 20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 21 * <http://www.gnu.org/licenses/>. 22 */ 23 24 /* %ecx */ 25 #define bit_SSE3 (1 << 0) 26 #define bit_PCLMUL (1 << 1) 27 #define bit_SSSE3 (1 << 9) 28 #define bit_FMA (1 << 12) 29 #define bit_CMPXCHG16B (1 << 13) 30 #define bit_SSE4_1 (1 << 19) 31 #define bit_SSE4_2 (1 << 20) 32 #define bit_POPCNT (1 << 23) 33 #define bit_AES (1 << 25) 34 #define bit_XSAVE (1 << 26) 35 #define bit_OSXSAVE (1 << 27) 36 #define bit_AVX (1 << 28) 37 38 /* %edx */ 39 #define bit_CMPXCHG8B (1 << 8) 40 #define bit_CMOV (1 << 15) 41 #define bit_MMX (1 << 23) 42 #define bit_FXSAVE (1 << 24) 43 #define bit_SSE (1 << 25) 44 #define bit_SSE2 (1 << 26) 45 46 /* Extended Features */ 47 /* %ecx */ 48 #define bit_LAHF_LM (1 << 0) 49 #define bit_SSE4a (1 << 6) 50 #define bit_SSE5 (1 << 11) 51 52 /* %edx */ 53 #define bit_LM (1 << 29) 54 #define bit_3DNOWP (1 << 30) 55 #define bit_3DNOW (1 << 31) 56 57 58 #if defined(__i386__) && defined(__PIC__) 59 /* %ebx may be the PIC register. */ 60 #if __GNUC__ >= 3 61 #define __cpuid(level, a, b, c, d) \ 62 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ 63 "cpuid\n\t" \ 64 "xchg{l}\t{%%}ebx, %1\n\t" \ 65 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 66 : "0" (level)) 67 68 #define __cpuid_count(level, count, a, b, c, d) \ 69 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ 70 "cpuid\n\t" \ 71 "xchg{l}\t{%%}ebx, %1\n\t" \ 72 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 73 : "0" (level), "2" (count)) 74 #else 75 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 76 nor alternatives in i386 code. */ 77 #define __cpuid(level, a, b, c, d) \ 78 __asm__ ("xchgl\t%%ebx, %1\n\t" \ 79 "cpuid\n\t" \ 80 "xchgl\t%%ebx, %1\n\t" \ 81 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 82 : "0" (level)) 83 84 #define __cpuid_count(level, count, a, b, c, d) \ 85 __asm__ ("xchgl\t%%ebx, %1\n\t" \ 86 "cpuid\n\t" \ 87 "xchgl\t%%ebx, %1\n\t" \ 88 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 89 : "0" (level), "2" (count)) 90 #endif 91 #else 92 #define __cpuid(level, a, b, c, d) \ 93 __asm__ ("cpuid\n\t" \ 94 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 95 : "0" (level)) 96 97 #define __cpuid_count(level, count, a, b, c, d) \ 98 __asm__ ("cpuid\n\t" \ 99 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 100 : "0" (level), "2" (count)) 101 #endif 102 103 /* Return highest supported input value for cpuid instruction. ext can 104 be either 0x0 or 0x8000000 to return highest supported value for 105 basic or extended cpuid information. Function returns 0 if cpuid 106 is not supported or whatever cpuid returns in eax register. If sig 107 pointer is non-null, then first four bytes of the signature 108 (as found in ebx register) are returned in location pointed by sig. */ 109 110 static __inline unsigned int 111 __get_cpuid_max (unsigned int __ext, unsigned int *__sig) 112 { 113 unsigned int __eax, __ebx, __ecx, __edx; 114 115 #ifndef __x86_64__ 116 #if __GNUC__ >= 3 117 /* See if we can use cpuid. On AMD64 we always can. */ 118 __asm__ ("pushf{l|d}\n\t" 119 "pushf{l|d}\n\t" 120 "pop{l}\t%0\n\t" 121 "mov{l}\t{%0, %1|%1, %0}\n\t" 122 "xor{l}\t{%2, %0|%0, %2}\n\t" 123 "push{l}\t%0\n\t" 124 "popf{l|d}\n\t" 125 "pushf{l|d}\n\t" 126 "pop{l}\t%0\n\t" 127 "popf{l|d}\n\t" 128 : "=&r" (__eax), "=&r" (__ebx) 129 : "i" (0x00200000)); 130 #else 131 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 132 nor alternatives in i386 code. */ 133 __asm__ ("pushfl\n\t" 134 "pushfl\n\t" 135 "popl\t%0\n\t" 136 "movl\t%0, %1\n\t" 137 "xorl\t%2, %0\n\t" 138 "pushl\t%0\n\t" 139 "popfl\n\t" 140 "pushfl\n\t" 141 "popl\t%0\n\t" 142 "popfl\n\t" 143 : "=&r" (__eax), "=&r" (__ebx) 144 : "i" (0x00200000)); 145 #endif 146 147 if (!((__eax ^ __ebx) & 0x00200000)) 148 return 0; 149 #endif 150 151 /* Host supports cpuid. Return highest supported cpuid input value. */ 152 __cpuid (__ext, __eax, __ebx, __ecx, __edx); 153 154 if (__sig) 155 *__sig = __ebx; 156 157 return __eax; 158 } 159 160 /* Return cpuid data for requested cpuid level, as found in returned 161 eax, ebx, ecx and edx registers. The function checks if cpuid is 162 supported and returns 1 for valid cpuid information or 0 for 163 unsupported cpuid level. All pointers are required to be non-null. */ 164 165 static __inline int 166 __get_cpuid (unsigned int __level, 167 unsigned int *__eax, unsigned int *__ebx, 168 unsigned int *__ecx, unsigned int *__edx) 169 { 170 unsigned int __ext = __level & 0x80000000; 171 172 if (__get_cpuid_max (__ext, 0) < __level) 173 return 0; 174 175 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); 176 return 1; 177 } 178
