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      1 /* Copyright (C) 2007-2008 The Android Open Source Project
      2 **
      3 ** This software is licensed under the terms of the GNU General Public
      4 ** License version 2, as published by the Free Software Foundation, and
      5 ** may be copied, distributed, and modified under those terms.
      6 **
      7 ** This program is distributed in the hope that it will be useful,
      8 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
      9 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     10 ** GNU General Public License for more details.
     11 */
     12 #include "qemu_file.h"
     13 #include "arm_pic.h"
     14 #include "goldfish_device.h"
     15 
     16 #define PDEV_BUS_OP_DONE        (0x00)
     17 #define PDEV_BUS_OP_REMOVE_DEV  (0x04)
     18 #define PDEV_BUS_OP_ADD_DEV     (0x08)
     19 
     20 #define PDEV_BUS_OP_INIT        (0x00)
     21 
     22 #define PDEV_BUS_OP             (0x00)
     23 #define PDEV_BUS_GET_NAME       (0x04)
     24 #define PDEV_BUS_NAME_LEN       (0x08)
     25 #define PDEV_BUS_ID             (0x0c)
     26 #define PDEV_BUS_IO_BASE        (0x10)
     27 #define PDEV_BUS_IO_SIZE        (0x14)
     28 #define PDEV_BUS_IRQ            (0x18)
     29 #define PDEV_BUS_IRQ_COUNT      (0x1c)
     30 
     31 struct bus_state {
     32     struct goldfish_device dev;
     33     struct goldfish_device *current;
     34 };
     35 
     36 qemu_irq *goldfish_pic;
     37 static struct goldfish_device *first_device;
     38 static struct goldfish_device *last_device;
     39 uint32_t goldfish_free_base;
     40 uint32_t goldfish_free_irq;
     41 
     42 void goldfish_device_set_irq(struct goldfish_device *dev, int irq, int level)
     43 {
     44     if(irq >= dev->irq_count)
     45         cpu_abort (cpu_single_env, "goldfish_device_set_irq: Bad irq %d >= %d\n", irq, dev->irq_count);
     46     else
     47         qemu_set_irq(goldfish_pic[dev->irq + irq], level);
     48 }
     49 
     50 int goldfish_add_device_no_io(struct goldfish_device *dev)
     51 {
     52     if(dev->base == 0) {
     53         dev->base = goldfish_free_base;
     54         goldfish_free_base += dev->size;
     55     }
     56     if(dev->irq == 0 && dev->irq_count > 0) {
     57         dev->irq = goldfish_free_irq;
     58         goldfish_free_irq += dev->irq_count;
     59     }
     60     //printf("goldfish_add_device: %s, base %x %x, irq %d %d\n",
     61     //       dev->name, dev->base, dev->size, dev->irq, dev->irq_count);
     62     dev->next = NULL;
     63     if(last_device) {
     64         last_device->next = dev;
     65     }
     66     else {
     67         first_device = dev;
     68     }
     69     last_device = dev;
     70     return 0;
     71 }
     72 
     73 int goldfish_device_add(struct goldfish_device *dev,
     74                        CPUReadMemoryFunc **mem_read,
     75                        CPUWriteMemoryFunc **mem_write,
     76                        void *opaque)
     77 {
     78     int iomemtype;
     79     goldfish_add_device_no_io(dev);
     80     iomemtype = cpu_register_io_memory(mem_read, mem_write, opaque);
     81     cpu_register_physical_memory(dev->base, dev->size, iomemtype);
     82     return 0;
     83 }
     84 
     85 static uint32_t goldfish_bus_read(void *opaque, target_phys_addr_t offset)
     86 {
     87     struct bus_state *s = (struct bus_state *)opaque;
     88 
     89     switch (offset) {
     90         case PDEV_BUS_OP:
     91             if(s->current) {
     92                 s->current->reported_state = 1;
     93                 s->current = s->current->next;
     94             }
     95             else {
     96                 s->current = first_device;
     97             }
     98             while(s->current && s->current->reported_state == 1)
     99                 s->current = s->current->next;
    100             if(s->current)
    101                 return PDEV_BUS_OP_ADD_DEV;
    102             else {
    103                 goldfish_device_set_irq(&s->dev, 0, 0);
    104                 return PDEV_BUS_OP_DONE;
    105             }
    106 
    107         case PDEV_BUS_NAME_LEN:
    108             return s->current ? strlen(s->current->name) : 0;
    109         case PDEV_BUS_ID:
    110             return s->current ? s->current->id : 0;
    111         case PDEV_BUS_IO_BASE:
    112             return s->current ? s->current->base : 0;
    113         case PDEV_BUS_IO_SIZE:
    114             return s->current ? s->current->size : 0;
    115         case PDEV_BUS_IRQ:
    116             return s->current ? s->current->irq : 0;
    117         case PDEV_BUS_IRQ_COUNT:
    118             return s->current ? s->current->irq_count : 0;
    119     default:
    120         cpu_abort (cpu_single_env, "goldfish_bus_read: Bad offset %x\n", offset);
    121         return 0;
    122     }
    123 }
    124 
    125 static void goldfish_bus_op_init(struct bus_state *s)
    126 {
    127     struct goldfish_device *dev = first_device;
    128     while(dev) {
    129         dev->reported_state = 0;
    130         dev = dev->next;
    131     }
    132     s->current = NULL;
    133     goldfish_device_set_irq(&s->dev, 0, first_device != NULL);
    134 }
    135 
    136 static void goldfish_bus_write(void *opaque, target_phys_addr_t offset, uint32_t value)
    137 {
    138     struct bus_state *s = (struct bus_state *)opaque;
    139 
    140     switch(offset) {
    141         case PDEV_BUS_OP:
    142             switch(value) {
    143                 case PDEV_BUS_OP_INIT:
    144                     goldfish_bus_op_init(s);
    145                     break;
    146                 default:
    147                     cpu_abort (cpu_single_env, "goldfish_bus_write: Bad PDEV_BUS_OP value %x\n", value);
    148             };
    149             break;
    150         case PDEV_BUS_GET_NAME:
    151             if(s->current)
    152                 cpu_memory_rw_debug(cpu_single_env, value, (void*)s->current->name, strlen(s->current->name), 1);
    153             break;
    154         default:
    155             cpu_abort (cpu_single_env, "goldfish_bus_write: Bad offset %x\n", offset);
    156     }
    157 }
    158 
    159 static CPUReadMemoryFunc *goldfish_bus_readfn[] = {
    160     goldfish_bus_read,
    161     goldfish_bus_read,
    162     goldfish_bus_read
    163 };
    164 
    165 static CPUWriteMemoryFunc *goldfish_bus_writefn[] = {
    166     goldfish_bus_write,
    167     goldfish_bus_write,
    168     goldfish_bus_write
    169 };
    170 
    171 
    172 static struct bus_state bus_state = {
    173     .dev = {
    174         .name = "goldfish_device_bus",
    175         .id = -1,
    176         .base = 0x10001000,
    177         .size = 0x1000,
    178         .irq = 1,
    179         .irq_count = 1,
    180     }
    181 };
    182 
    183 void goldfish_device_init(qemu_irq *pic, uint32_t base, uint32_t size, uint32_t irq, uint32_t irq_count)
    184 {
    185     goldfish_pic = pic;
    186     goldfish_free_base = base;
    187     goldfish_free_irq = irq;
    188 }
    189 
    190 int goldfish_device_bus_init(uint32_t base, uint32_t irq)
    191 {
    192     bus_state.dev.base = base;
    193     bus_state.dev.irq = irq;
    194 
    195     return goldfish_device_add(&bus_state.dev, goldfish_bus_readfn, goldfish_bus_writefn, &bus_state);
    196 }
    197 
    198