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Searched
refs:eeprom
(Results
1 - 5
of
5
) sorted by null
/external/grub/netboot/
3c90x.c
292
/*** a3c90x_internal_ReadEeprom - read data from the serial
eeprom
.
302
/** Make sure the
eeprom
isn't busy **/
315
*** data to the onboard serial
eeprom
(not the BIOS prom, but the
325
/** Verify
Eeprom
not busy **/
336
/** Send the new data to the
eeprom
, and wait for completion. **/
341
/** Burn the new data into the
eeprom
, and wait for completion. **/
349
/*** a3c90x_internal_WriteEeprom - write data to the serial
eeprom
,
350
*** and re-compute the
eeprom
checksum.
381
/** Write the checksum to the location in the
eeprom
**/
683
unsigned short
eeprom
[0x21]
local
[
all
...]
eepro100.c
119
SCBflash = 12, SCBeeprom = 14, /*
EEPROM
and flash memory control. */
131
/* Serial
EEPROM
section.
134
#define EE_SHIFT_CLK 0x01 /*
EEPROM
shift clock. */
135
#define EE_CS 0x02 /*
EEPROM
chip select. */
136
#define EE_DATA_WRITE 0x04 /*
EEPROM
chip data in. */
137
#define EE_DATA_READ 0x08 /*
EEPROM
chip data out. */
144
/* The
EEPROM
commands include the alway-set leading bit. */
315
<visitor@valinux.com> to strictly follow Intel specifications of
EEPROM
318
interval for serial
EEPROM
. However, it looks like that there is an
338
/* Terminate the
EEPROM
access. *
492
unsigned short
eeprom
[16];
local
[
all
...]
epic100.c
80
static unsigned short
eeprom
[64];
variable
128
eectl = ioaddr + EECTL; /*
EEPROM
Control */
165
eeprom
[i] = value;
170
printf("
EEPROM
contents\n");
172
printf(" %hhX%s",
eeprom
[i], i % 16 == 15 ? "\n" : "");
177
/* This could also be read from the
EEPROM
. */
411
/* Serial
EEPROM
section. */
414
#define EE_SHIFT_CLK 0x04 /*
EEPROM
shift clock. */
415
#define EE_CS 0x02 /*
EEPROM
chip select. */
416
#define EE_DATA_WRITE 0x08 /*
EEPROM
chip data in. *
[
all
...]
w89c840.c
262
static unsigned short
eeprom
[0x40];
variable
648
/* Ok. Got one. Read the
eeprom
. */
651
eeprom
[i] = value;
656
nic->node_addr[i] = (
eeprom
[i/2] >> (8*(i&1))) & 0xff;
661
printf("winbond-840:
EEPROM
checksum %hX, got
eeprom
", sum);
702
/* Read the
EEPROM
and MII Management Data I/O (MDIO) interfaces. These are
704
The example below is for the common 93c46
EEPROM
, 64 16 bit words. */
706
/* Delay between
EEPROM
clock transitions.
720
/* The
EEPROM
commands include the alway-set leading bit. *
[
all
...]
tulip.c
329
/*
EEPROM
Address width definitions */
333
/* The
EEPROM
commands include the alway-set leading bit. */
339
#define EE_SHIFT_CLK 0x02 /*
EEPROM
shift clock. */
340
#define EE_CS 0x01 /*
EEPROM
chip select. */
341
#define EE_DATA_WRITE 0x04 /*
EEPROM
chip data in. */
344
#define EE_DATA_READ 0x08 /*
EEPROM
chip data out. */
347
/* Delay between
EEPROM
clock transitions. Even at 33Mhz current PCI
348
implementations don't overrun the
EEPROM
clock. We add a bus
422
unsigned char
eeprom
[EEPROM_SIZE]; /* Serial
EEPROM
contents. *
421
unsigned char
eeprom
[EEPROM_SIZE]; \/* Serial EEPROM contents. *\/
member in struct:tulip_private
[
all
...]
Completed in 162 milliseconds