Lines Matching defs:val
353 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
356 env->ZF = (~val) & CPSR_Z;
357 env->NF = val;
358 env->CF = (val >> 29) & 1;
359 env->VF = (val << 3) & 0x80000000;
362 env->QF = ((val & CPSR_Q) != 0);
364 env->thumb = ((val & CPSR_T) != 0);
367 env->condexec_bits |= (val >> 25) & 3;
371 env->condexec_bits |= (val >> 8) & 0xfc;
374 env->GE = (val >> 16) & 0xf;
377 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
378 switch_mode(env, val & CPSR_M);
381 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
535 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
549 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
561 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
578 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
643 static void v7m_push(CPUARMState *env, uint32_t val)
646 stl_phys(env->regs[13], val);
651 uint32_t val;
652 val = ldl_phys(env->regs[13]);
654 return val;
1277 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
1286 cp_info, src, operand, val);
1303 static uint32_t simple_mpu_ap_bits(uint32_t val)
1311 ret |= (val >> i) & mask;
1318 static uint32_t extended_mpu_ap_bits(uint32_t val)
1326 ret |= (val & mask) << i;
1332 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1350 env->cp15.c0_cssel = val & 0xf;
1360 env->cp15.c1_sys = val;
1367 env->cp15.c1_xscaleauxcr = val;
1375 if (env->cp15.c1_coproc != val) {
1376 env->cp15.c1_coproc = val;
1389 env->cp15.c2_data = val;
1392 env->cp15.c2_insn = val;
1400 env->cp15.c2_base0 = val;
1403 env->cp15.c2_base1 = val;
1406 val &= 7;
1407 env->cp15.c2_control = val;
1408 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1409 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1417 env->cp15.c3 = val;
1428 val = extended_mpu_ap_bits(val);
1429 env->cp15.c5_data = val;
1433 val = extended_mpu_ap_bits(val);
1434 env->cp15.c5_insn = val;
1439 env->cp15.c5_data = val;
1444 env->cp15.c5_insn = val;
1454 env->cp15.c6_region[crm] = val;
1460 env->cp15.c6_data = val;
1464 env->cp15.c6_insn = val;
1487 val &= 0xfffff000;
1488 tlb_flush_page(env, val);
1489 tlb_flush_page(env, val + 0x400);
1490 tlb_flush_page(env, val + 0x800);
1491 tlb_flush_page(env, val + 0xc00);
1497 tlb_flush(env, val == 0);
1516 env->cp15.c9_data = val;
1519 env->cp15.c9_insn = val;
1550 if (env->cp15.c13_fcse != val)
1552 env->cp15.c13_fcse = val;
1556 if (env->cp15.c13_context != val
1559 env->cp15.c13_context = val;
1562 env->cp15.c13_tls1 = val;
1565 env->cp15.c13_tls2 = val;
1568 env->cp15.c13_tls3 = val;
1579 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1582 env->cp15.c15_cpar = val & 0x3fff;
1593 env->cp15.c15_ticonfig = val & 0xe7;
1594 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1598 env->cp15.c15_i_max = val;
1601 env->cp15.c15_i_min = val;
1604 env->cp15.c15_threadid = val & 0xffff;
1891 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
1893 env->banked_r13[bank_number(mode)] = val;
1938 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
1942 xpsr_write(env, val, 0xf8000000);
1945 xpsr_write(env, val, 0xf8000000);
1948 xpsr_write(env, val, 0xfe00fc00);
1951 xpsr_write(env, val, 0xfe00fc00);
1957 xpsr_write(env, val, 0x0600fc00);
1960 xpsr_write(env, val, 0x0600fc00);
1964 env->v7m.other_sp = val;
1966 env->regs[13] = val;
1970 env->regs[13] = val;
1972 env->v7m.other_sp = val;
1975 if (val & 1)
1981 if (val & 1)
1987 env->v7m.basepri = val & 0xff;
1990 val &= 0xff;
1991 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1992 env->v7m.basepri = val;
1995 env->v7m.control = val & 3;
1996 switch_v7m_sp(env, (val & 2) != 0);
2265 uint32_t HELPER(logicq_cc)(uint64_t val)
2267 return (val >> 32) | (val != 0);
2323 void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2329 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2330 env->vfp.vec_len = (val >> 16) & 7;
2331 env->vfp.vec_stride = (val >> 20) & 3;
2333 changed ^= val;
2335 i = (val
2353 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2355 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2357 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2665 void HELPER(set_teecr)(CPUState *env, uint32_t val)
2667 val &= 1;
2668 if (env->teecr != val) {
2669 env->teecr = val;
