Lines Matching refs:Instr
62 void Stop(Instr* instr);
77 bool SetBreakpoint(Instr* breakpc);
78 bool DeleteBreakpoint(Instr* breakpc);
109 void Debugger::Stop(Instr* instr) {
110 char* str = reinterpret_cast<char*>(instr->InstructionBits() & 0x0fffffff);
116 instr->SetInstructionBits(0xe1a00000); // Overwrite with nop.
118 sim_->set_pc(sim_->get_pc() + Instr::kInstrSize);
127 void Debugger::Stop(Instr* instr) {
128 const char* str = (const char*)(instr->InstructionBits() & 0x0fffffff);
130 sim_->set_pc(sim_->get_pc() + Instr::kInstrSize);
157 bool Debugger::SetBreakpoint(Instr* breakpc) {
172 bool Debugger::DeleteBreakpoint(Instr* breakpc) {
243 sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
246 sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
297 end = cur + (10 * Instr::kInstrSize);
303 end = cur + (10 * Instr::kInstrSize);
310 end = cur + (value2 * Instr::kInstrSize);
317 cur += Instr::kInstrSize;
327 if (!SetBreakpoint(reinterpret_cast<Instr*>(value))) {
351 intptr_t stop_pc = sim_->get_pc() - Instr::kInstrSize;
352 Instr* stop_instr = reinterpret_cast<Instr*>(stop_pc);
505 static Redirection* FromSwiInstruction(Instr* swi_instruction) {
560 return registers_[reg] + ((reg == pc) ? Instr::kPCReadOffset : 0);
709 int Simulator::ReadW(int32_t addr, Instr* instr) {
720 void Simulator::WriteW(int32_t addr, int value, Instr* instr) {
726 PrintF("Unaligned write at 0x%08x, pc=%p\n", addr, instr);
731 uint16_t Simulator::ReadHU(int32_t addr, Instr* instr) {
736 PrintF("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr, instr);
742 int16_t Simulator::ReadH(int32_t addr, Instr* instr) {
753 void Simulator::WriteH(int32_t addr, uint16_t value, Instr* instr) {
759 PrintF("Unaligned unsigned halfword write at 0x%08x, pc=%p\n", addr, instr);
764 void Simulator::WriteH(int32_t addr, int16_t value, Instr* instr) {
770 PrintF("Unaligned halfword write at 0x%08x, pc=%p\n", addr, instr);
808 void Simulator::Format(Instr* instr, const char* format) {
810 instr, format);
817 bool Simulator::ConditionallyExecute(Instr* instr) {
818 switch (instr->ConditionField()) {
935 int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) {
936 Shift shift = instr->ShiftField();
937 int shift_amount = instr->ShiftAmountField();
938 int32_t result = get_register(instr->RmField());
939 if (instr->Bit(4) == 0) {
1002 int rs = instr->RsField();
1079 int32_t Simulator::GetImm(Instr* instr, bool* carry_out) {
1080 instr->RotateField() * 2;
1081 int immed8 = instr->Immed8Field();
1101 void Simulator::HandleRList(Instr* instr, bool load) {
1102 int rn = instr->RnField();
1104 int rlist = instr->RlistField();
1109 switch (instr->PUField()) {
1139 if (instr->HasW()) {
1178 void Simulator::SoftwareInterrupt(Instr* instr) {
1179 int swi = instr->SwiField();
1182 Redirection* redirection = Redirection::FromSwiInstruction(instr);
1247 void Simulator::DecodeType01(Instr* instr) {
1248 int type = instr->TypeField();
1249 if ((type == 0) && instr->IsSpecialType0()) {
1251 if (instr->Bits(7, 4) == 9) {
1252 if (instr->Bit(24) == 0) {
1255 int rn = instr->RnField();
1256 int rm = instr->RmField();
1257 int rs = instr->RsField();
1260 if (instr->Bit(23) == 0) {
1261 if (instr->Bit(21) == 0) {
1265 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
1269 if (instr->HasS()) {
1277 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
1289 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
1291 int rd_lo = instr->RdField();
1294 if (instr->Bit(22) == 1) {
1310 if (instr->HasS()) {
1319 int rd = instr->RdField();
1320 int rn = instr->RnField();
1323 if (instr->Bit(22) == 0) {
1324 int rm = instr->RmField();
1326 switch (instr->PUField()) {
1328 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
1329 ASSERT(!instr->HasW());
1336 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
1337 ASSERT(!instr->HasW());
1344 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
1347 if (instr->HasW()) {
1353 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
1356 if (instr->HasW()) {
1368 int32_t imm_val = (instr->ImmedHField() << 4) | instr->ImmedLField();
1369 switch (instr->PUField()) {
1371 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
1372 ASSERT(!instr->HasW());
1379 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
1380 ASSERT(!instr->HasW());
1387 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
1390 if (instr->HasW()) {
1396 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
1399 if (instr->HasW()) {
1411 if (instr->HasH()) {
1412 if (instr->HasSign()) {
1413 if (instr->HasL()) {
1414 int16_t val = ReadH(addr, instr);
1418 WriteH(addr, val, instr);
1421 if (instr->HasL()) {
1422 uint16_t val = ReadHU(addr, instr);
1426 WriteH(addr, val, instr);
1431 ASSERT(instr->HasSign());
1432 ASSERT(instr->HasL());
1439 int rd = instr->RdField();
1440 int rn = instr->RnField();
1445 shifter_operand = GetShiftRm(instr, &shifter_carry_out);
1447 ASSERT(instr->TypeField() == 1);
1448 shifter_operand = GetImm(instr, &shifter_carry_out);
1452 switch (instr->OpcodeField()) {
1454 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
1455 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
1458 if (instr->HasS()) {
1466 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
1467 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
1470 if (instr->HasS()) {
1478 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
1479 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
1482 if (instr->HasS()) {
1491 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
1492 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
1495 if (instr->HasS()) {
1504 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
1505 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
1508 if (instr->HasS()) {
1517 Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
1518 Format(instr, "adc'cond's 'rd, 'rn, 'imm");
1523 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
1524 Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
1529 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
1530 Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
1535 if (instr->HasS()) {
1536 // Format(instr, "tst'cond 'rn, 'shift_rm");
1537 // Format(instr, "tst'cond 'rn, 'imm");
1548 if (instr->HasS()) {
1549 // Format(instr, "teq'cond 'rn, 'shift_rm");
1550 // Format(instr, "teq'cond 'rn, 'imm");
1556 int rm = instr->RmField();
1557 switch (instr->Bits(7, 4)) {
1564 set_register(lr, old_pc + Instr::kInstrSize);
1575 if (instr->HasS()) {
1576 // Format(instr, "cmp'cond 'rn, 'shift_rm");
1577 // Format(instr, "cmp'cond 'rn, 'imm");
1589 if (instr->HasS()) {
1590 // Format(instr, "cmn'cond 'rn, 'shift_rm");
1591 // Format(instr, "cmn'cond 'rn, 'imm");
1598 int rm = instr->RmField();
1599 int rd = instr->RdField();
1600 switch (instr->Bits(7, 4)) {
1623 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
1624 // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
1627 if (instr->HasS()) {
1635 // Format(instr, "mov'cond's 'rd, 'shift_rm");
1636 // Format(instr, "mov'cond's 'rd, 'imm");
1639 if (instr->HasS()) {
1647 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
1648 // Format(instr, "bic'cond's 'rd, 'rn, 'imm");
1651 if (instr->HasS()) {
1659 // Format(instr, "mvn'cond's 'rd, 'shift_rm");
1660 // Format(instr, "mvn'cond's 'rd, 'imm");
1663 if (instr->HasS()) {
1679 void Simulator::DecodeType2(Instr* instr) {
1680 int rd = instr->RdField();
1681 int rn = instr->RnField();
1683 int32_t im_val = instr->Offset12Field();
1685 switch (instr->PUField()) {
1687 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
1688 ASSERT(!instr->HasW());
1695 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
1696 ASSERT(!instr->HasW());
1703 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
1706 if (instr->HasW()) {
1712 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
1715 if (instr->HasW()) {
1725 if (instr->HasB()) {
1726 if (instr->HasL()) {
1734 if (instr->HasL()) {
1735 set_register(rd, ReadW(addr, instr));
1737 WriteW(addr, get_register(rd), instr);
1743 void Simulator::DecodeType3(Instr* instr) {
1744 ASSERT(instr->Bits(6, 4) == 0x5 || instr->Bit(4) == 0);
1745 int rd = instr->RdField();
1746 int rn = instr->RnField();
1749 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
1751 switch (instr->PUField()) {
1753 ASSERT(!instr->HasW());
1754 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
1758 ASSERT(!instr->HasW());
1759 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
1763 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
1765 if (instr->HasW()) {
1771 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
1772 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
1773 uint32_t lsbit = static_cast<uint32_t>(instr->ShiftAmountField());
1777 static_cast<uint32_t>(get_register(instr->RmField()));
1780 set_register(instr->RdField(), extr_val);
1786 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
1788 if (instr->HasW()) {
1799 if (instr->HasB()) {
1800 if (instr->HasL()) {
1808 if (instr->HasL()) {
1809 set_register(rd, ReadW(addr, instr));
1811 WriteW(addr, get_register(rd), instr);
1817 void Simulator::DecodeType4(Instr* instr) {
1818 ASSERT(instr->Bit(22) == 0); // only allowed to be set in privileged mode
1819 if (instr->HasL()) {
1820 // Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
1821 HandleRList(instr, true);
1823 // Format(instr, "stm'cond'pu 'rn'w, 'rlist");
1824 HandleRList(instr, false);
1829 void Simulator::DecodeType5(Instr* instr) {
1830 // Format(instr, "b'l'cond 'target");
1831 int off = (instr->SImmed24Field() << 2);
1833 if (instr->HasLink()) {
1834 set_register(lr, pc_address + Instr::kInstrSize);
1841 void Simulator::DecodeType6(Instr* instr) {
1842 DecodeType6CoprocessorIns(instr);
1846 void Simulator::DecodeType7(Instr* instr) {
1847 if (instr->Bit(24) == 1) {
1848 SoftwareInterrupt(instr);
1850 DecodeTypeVFP(instr);
1855 void Simulator::DecodeUnconditional(Instr* instr) {
1856 if (instr->Bits(7, 4) == 0x0B && instr->Bits(27, 25) == 0 && instr->HasL()) {
1858 int rd = instr->RdField();
1859 int rn = instr->RnField();
1863 if (instr->Bit(22) == 0) {
1865 int rm = instr->RmField();
1869 offset = instr->Bits(3, 0) + (instr->Bits(11, 8) << 4);
1871 switch (instr->PUField()) {
1874 ASSERT(!instr->HasW());
1882 ASSERT(!instr->HasW());
1892 if (instr->HasW()) {
1901 if (instr->HasW()) {
1913 uint16_t halfword = ReadH(addr, instr);
1917 dbg.Stop(instr);
1922 // void Simulator::DecodeTypeVFP(Instr* instr)
1934 void Simulator::DecodeTypeVFP(Instr* instr) {
1935 ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) );
1937 int rt = instr->RtField();
1938 int vm = instr->VmField();
1939 int vn = instr->VnField();
1940 int vd = instr->VdField();
1942 if (instr->Bit(23) == 1) {
1943 if ((instr->Bits(21, 19) == 0x7) &&
1944 (instr->Bits(18, 16) == 0x5) &&
1945 (instr->Bits(11, 9) == 0x5) &&
1946 (instr->Bit(8) == 1) &&
1947 (instr->Bit(6) == 1) &&
1948 (instr->Bit(4) == 0)) {
1951 set_s_register_from_sinteger(((vd<<1) | instr->DField()), int_value);
1952 } else if ((instr->Bits(21, 19) == 0x7) &&
1953 (instr->Bits(18, 16) == 0x0) &&
1954 (instr->Bits(11, 9) == 0x5) &&
1955 (instr->Bit(8) == 1) &&
1956 (instr->Bit(7) == 1) &&
1957 (instr->Bit(6) == 1) &&
1958 (instr->Bit(4) == 0)) {
1960 instr->MField()));
1963 } else if ((instr->Bit(21) == 0x0) &&
1964 (instr->Bit(20) == 0x0) &&
1965 (instr->Bits(11, 9) == 0x5) &&
1966 (instr->Bit(8) == 1) &&
1967 (instr->Bit(6) == 0) &&
1968 (instr->Bit(4) == 0)) {
1973 } else if ((instr->Bits(21, 20) == 0x3) &&
1974 (instr->Bits(19, 16) == 0x4) &&
1975 (instr->Bits(11, 9) == 0x5) &&
1976 (instr->Bit(8) == 0x1) &&
1977 (instr->Bit(6) == 0x1) &&
1978 (instr->Bit(4) == 0x0)) {
1982 } else if ((instr->Bits(23, 20) == 0xF) &&
1983 (instr->Bits(19, 16) == 0x1) &&
1984 (instr->Bits(11, 8) == 0xA) &&
1985 (instr->Bits(7, 5) == 0x0) &&
1986 (instr->Bit(4) == 0x1) &&
1987 (instr->Bits(3, 0) == 0x0)) {
1988 if (instr->Bits(15, 12) == 0xF)
1995 } else if (instr->Bit(21) == 1) {
1996 if ((instr->Bit(20) == 0x1) &&
1997 (instr->Bits(11, 9) == 0x5) &&
1998 (instr->Bit(8) == 0x1) &&
1999 (instr->Bit(6) == 0) &&
2000 (instr->Bit(4) == 0)) {
2005 } else if ((instr->Bit(20) == 0x1) &&
2006 (instr->Bits(11, 9) == 0x5) &&
2007 (instr->Bit(8) == 0x1) &&
2008 (instr->Bit(6) == 1) &&
2009 (instr->Bit(4) == 0)) {
2014 } else if ((instr->Bit(20) == 0x0) &&
2015 (instr->Bits(11, 9) == 0x5) &&
2016 (instr->Bit(8) == 0x1) &&
2017 (instr->Bit(6) == 0) &&
2018 (instr->Bit(4) == 0)) {
2027 if ((instr->Bit(20) == 0x0) &&
2028 (instr->Bits(11, 8) == 0xA) &&
2029 (instr->Bits(6, 5) == 0x0) &&
2030 (instr->Bit(4) == 1) &&
2031 (instr->Bits(3, 0) == 0x0)) {
2033 set_s_register_from_sinteger(((vn<<1) | instr->NField()), rs_val);
2034 } else if ((instr->Bit(20) == 0x1) &&
2035 (instr->Bits(11, 8) == 0xA) &&
2036 (instr->Bits(6, 5) == 0x0) &&
2037 (instr->Bit(4) == 1) &&
2038 (instr->Bits(3, 0) == 0x0)) {
2040 instr->NField()));
2049 // void Simulator::DecodeType6CoprocessorIns(Instr* instr)
2055 void Simulator::DecodeType6CoprocessorIns(Instr* instr) {
2056 ASSERT((instr->TypeField() == 6));
2058 if (instr->CoprocessorField() != 0xB) {
2061 switch (instr->OpcodeField()) {
2064 if (instr->Bits(7, 4) != 0x1) {
2067 int rt = instr->RtField();
2068 int rn = instr->RnField();
2069 int vm = instr->VmField();
2070 if (instr->HasL()) {
2087 int rn = instr->RnField();
2088 int vd = instr->VdField();
2089 int offset = instr->Immed8Field();
2090 if (!instr->HasU()) {
2094 if (instr->HasL()) {
2096 set_s_register_from_sinteger(2*vd, ReadW(address, instr));
2097 set_s_register_from_sinteger(2*vd + 1, ReadW(address + 4, instr));
2100 WriteW(address, get_sinteger_from_s_register(2*vd), instr);
2101 WriteW(address + 4, get_sinteger_from_s_register(2*vd + 1), instr);
2114 void Simulator::InstructionDecode(Instr* instr) {
2122 reinterpret_cast<byte*>(instr));
2123 PrintF(" 0x%08x %s\n", instr, buffer.start());
2125 if (instr->ConditionField() == special_condition) {
2126 DecodeUnconditional(instr);
2127 } else if (ConditionallyExecute(instr)) {
2128 switch (instr->TypeField()) {
2131 DecodeType01(instr);
2135 DecodeType2(instr);
2139 DecodeType3(instr);
2143 DecodeType4(instr);
2147 DecodeType5(instr);
2151 instr);
2155 DecodeType7(instr);
2165 set_register(pc, reinterpret_cast<int32_t>(instr) + Instr::kInstrSize);
2179 Instr* instr = reinterpret_cast<Instr*>(program_counter);
2181 InstructionDecode(instr);
2188 Instr* instr = reinterpret_cast<Instr*>(program_counter);
2194 InstructionDecode(instr);
