Lines Matching refs:rd
459 Register rd,
462 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
464 | (rd.code() << kRdShift) | (sa << kSaShift) | func;
641 void Assembler::jalr(Register rs, Register rd) {
642 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
650 void Assembler::add(Register rd, Register rs, Register rt) {
651 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADD);
655 void Assembler::addu(Register rd, Register rs, Register rt) {
656 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
660 void Assembler::addi(Register rd, Register rs, int32_t j) {
661 GenInstrImmediate(ADDI, rs, rd, j);
665 void Assembler::addiu(Register rd, Register rs, int32_t j) {
666 GenInstrImmediate(ADDIU, rs, rd, j);
670 void Assembler::sub(Register rd, Register rs, Register rt) {
671 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUB);
675 void Assembler::subu(Register rd, Register rs, Register rt) {
676 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
680 void Assembler::mul(Register rd, Register rs, Register rt) {
681 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
707 void Assembler::and_(Register rd, Register rs, Register rt) {
708 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
717 void Assembler::or_(Register rd, Register rs, Register rt) {
718 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
727 void Assembler::xor_(Register rd, Register rs, Register rt) {
728 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
737 void Assembler::nor(Register rd, Register rs, Register rt) {
738 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
743 void Assembler::sll(Register rd, Register rt, uint16_t sa) {
744 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
748 void Assembler::sllv(Register rd, Register rt, Register rs) {
749 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
753 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
754 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
758 void Assembler::srlv(Register rd, Register rt, Register rs) {
759 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
763 void Assembler::sra(Register rd, Register rt, uint16_t sa) {
764 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
768 void Assembler::srav(Register rd, Register rt, Register rs) {
769 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
775 void Assembler::lb(Register rd, const MemOperand& rs) {
776 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
780 void Assembler::lbu(Register rd, const MemOperand& rs) {
781 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
785 void Assembler::lw(Register rd, const MemOperand& rs) {
786 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
790 void Assembler::sb(Register rd, const MemOperand& rs) {
791 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
795 void Assembler::sw(Register rd, const MemOperand& rs) {
796 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
800 void Assembler::lui(Register rd, int32_t j) {
801 GenInstrImmediate(LUI, zero_reg, rd, j);
865 void Assembler::mfhi(Register rd) {
866 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
870 void Assembler::mflo(Register rd) {
871 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
876 void Assembler::slt(Register rd, Register rs, Register rt) {
877 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
881 void Assembler::sltu(Register rd, Register rs, Register rt) {
882 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
