Lines Matching defs:ARMRegisters
40 namespace ARMRegisters {
73 } // namespace ARMRegisters
77 typedef ARMRegisters::RegisterID RegisterID;
78 typedef ARMRegisters::FPRegisterID FPRegisterID;
343 emitInst(static_cast<ARMWord>(cc) | MOV, rd, ARMRegisters::r0, op2);
362 emitInst(static_cast<ARMWord>(cc) | MOV | SET_CC, rd, ARMRegisters::r0, op2);
377 emitInst(static_cast<ARMWord>(cc) | MVN, rd, ARMRegisters::r0, op2);
382 emitInst(static_cast<ARMWord>(cc) | MVN | SET_CC, rd, ARMRegisters::r0, op2);
427 m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm, true);
432 m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm);
490 m_buffer.putInt(cc | DTR | DT_WB | RN(ARMRegisters::sp) | RD(reg) | 0x4);
496 m_buffer.putInt(cc | (DTR ^ DT_PRE) | DT_LOAD | DT_UP | RN(ARMRegisters::sp) | RD(reg) | 0x4);
501 dtr_d(false, ARMRegisters::sp, 0, reg, cc);
506 dtr_u(true, reg, ARMRegisters::sp, 0, cc);
547 dtr_dr(true, ARMRegisters::S0, ARMRegisters::S0, ARMRegisters::S0);
553 ASSERT(reg <= ARMRegisters::pc);
560 ASSERT(reg <= ARMRegisters::pc);
567 ASSERT(reg <= ARMRegisters::pc);
574 ASSERT(reg <= ARMRegisters::pc);
575 ASSERT(shiftReg <= ARMRegisters::pc);
581 ASSERT(reg <= ARMRegisters::pc);
582 ASSERT(shiftReg <= ARMRegisters::pc);
588 ASSERT(reg <= ARMRegisters::pc);
589 ASSERT(shiftReg <= ARMRegisters::pc);
618 mov_r(ARMRegisters::r0, ARMRegisters::r0);
627 ldr_un_imm(ARMRegisters::pc, 0xffffffff, cc);
799 ASSERT(reg <= ARMRegisters::pc);
805 ASSERT(reg <= ARMRegisters::pc);
811 ASSERT(reg <= ARMRegisters::pc);
817 ASSERT(reg <= ARMRegisters::pc);
