Lines Matching refs:m_assembler
86 m_assembler.adds_r(dest, dest, src);
98 m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
109 m_assembler.ands_r(dest, dest, src);
114 ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
116 m_assembler.bics_r(dest, dest, w & ~ARMAssembler::OP2_INV_IMM);
118 m_assembler.ands_r(dest, dest, w);
125 m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
127 m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));
132 m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
141 m_assembler.muls_r(dest, dest, src);
147 m_assembler.muls_r(dest, src, ARMRegisters::S0);
152 m_assembler.rsbs_r(srcDest, srcDest, ARMAssembler::getOp2(0));
157 m_assembler.mvns_r(dest, dest);
162 m_assembler.orrs_r(dest, dest, src);
167 m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
174 m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
176 m_assembler.movs_r(dest, m_assembler.asr_r(dest, ARMRegisters::S0));
181 m_assembler.movs_r(dest, m_assembler.asr(dest, imm.m_value & 0x1f));
186 m_assembler.subs_r(dest, dest, src);
191 m_assembler.subs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
209 m_assembler.eors_r(dest, dest, src);
214 m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
219 m_assembler.dataTransfer32(true, dest, address.base, address.offset);
224 m_assembler.baseIndexTransfer32(true, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
239 m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
240 m_assembler.dtr_ur(true, dest, address.base, ARMRegisters::S0);
253 m_assembler.add_r(ARMRegisters::S0, address.base, m_assembler.lsl(address.index, address.scale));
255 m_assembler.ldrh_u(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(address.offset));
257 m_assembler.ldrh_d(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(-address.offset));
263 m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
264 m_assembler.dtr_ur(false, src, address.base, ARMRegisters::S0);
270 m_assembler.dataTransfer32(false, src, address.base, address.offset);
275 m_assembler.baseIndexTransfer32(false, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
281 m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);
289 m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
290 m_assembler.dtr_u(false, src, ARMRegisters::S0, 0);
295 m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
297 m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);
299 m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
300 m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
305 m_assembler.pop_r(dest);
310 m_assembler.push_r(src);
328 m_assembler.ldr_un_imm(dest, imm.m_value);
330 m_assembler.moveImm(imm.m_value, dest);
335 m_assembler.mov_r(dest, src);
345 m_assembler.mov_r(ARMRegisters::S0, reg1);
346 m_assembler.mov_r(reg1, reg2);
347 m_assembler.mov_r(reg2, ARMRegisters::S0);
364 m_assembler.cmp_r(left, right);
365 return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
371 m_assembler.ldr_un_imm(ARMRegisters::S0, right.m_value);
372 m_assembler.cmp_r(left, ARMRegisters::S0);
374 m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
375 return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
421 m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S1);
422 return m_assembler.jmp(ARMCondition(cond));
428 m_assembler.tst_r(reg, mask);
429 return Jump(m_assembler.jmp(ARMCondition(cond)));
435 ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);
437 m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::OP2_INV_IMM);
439 m_assembler.tst_r(reg, w);
440 return Jump(m_assembler.jmp(ARMCondition(cond)));
457 return Jump(m_assembler.jmp());
474 return Jump(m_assembler.jmp(ARMCondition(cond)));
481 return Jump(m_assembler.jmp(ARMCondition(cond)));
490 m_assembler.mull_r(ARMRegisters::S1, dest, src2, src1);
491 m_assembler.cmp_r(ARMRegisters::S1, m_assembler.asr(dest, 31));
503 return Jump(m_assembler.jmp(ARMCondition(cond)));
516 return Jump(m_assembler.jmp(ARMCondition(cond)));
523 return Jump(m_assembler.jmp(ARMCondition(cond)));
530 return Jump(m_assembler.jmp(ARMCondition(cond)));
537 return Jump(m_assembler.jmp(ARMCondition(cond)));
542 m_assembler.bkpt(0);
548 return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::LinkableNear);
566 m_assembler.mov_r(ARMRegisters::pc, linkRegister);
571 m_assembler.cmp_r(left, right);
572 m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
573 m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
578 m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
579 m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
580 m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
606 m_assembler.cmp_r(0, ARMRegisters::S1);
608 m_assembler.tst_r(ARMRegisters::S1, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
609 m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
610 m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
621 m_assembler.add_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
626 m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
627 m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
629 m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
630 m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
635 m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
636 m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
638 m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
639 m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
644 m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
645 m_assembler.dtr_u(true, dest, ARMRegisters::S0, 0);
663 return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::Linkable);
679 m_assembler.ldr_un_imm(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
723 m_assembler.doubleTransfer(true, dest, address.base, address.offset);
728 m_assembler.ldr_un_imm(ARMRegisters::S0, (ARMWord)address);
729 m_assembler.fdtr_u(true, dest, ARMRegisters::S0, 0);
734 m_assembler.doubleTransfer(false, src, address.base, address.offset);
739 m_assembler.faddd_r(dest, dest, src);
750 m_assembler.fdivd_r(dest, dest, src);
762 m_assembler.fsubd_r(dest, dest, src);
773 m_assembler.fmuld_r(dest, dest, src);
784 m_assembler.fmsr_r(dest, src);
785 m_assembler.fsitod_r(dest, dest);
800 m_assembler.ldr_un_imm(ARMRegisters::S1, (ARMWord)src.m_ptr);
801 m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
807 m_assembler.fcmpd_r(left, right);
808 m_assembler.fmstat();
810 m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
811 return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
832 m_assembler.ftosid_r(ARMRegisters::SD0, src);
833 m_assembler.fmrs_r(dest, ARMRegisters::SD0);
836 m_assembler.fsitod_r(ARMRegisters::SD0, ARMRegisters::SD0);
845 m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2(0));
857 m_assembler.ensureSpace(insnSpace, constSpace);
862 return m_assembler.sizeOfConstantPool();
869 m_assembler.mov_r(linkRegister, ARMRegisters::pc);
880 m_assembler.dtr_u(true, ARMRegisters::pc, base, offset);
882 m_assembler.add_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
884 m_assembler.dtr_u(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);
886 ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
888 m_assembler.dtr_ur(true, ARMRegisters::pc, base, reg);
894 m_assembler.dtr_d(true, ARMRegisters::pc, base, offset);
896 m_assembler.sub_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
898 m_assembler.dtr_d(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);
900 ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
902 m_assembler.dtr_dr(true, ARMRegisters::pc, base, reg);
