Lines Matching refs:rev
62 uint8 rev; /* PCI Card Revision ID */
87 si->rev = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_REV, 4) & 0xFF;
89 if (si->rev < 3) {
90 sd_err(("Host controller %d not supported, please upgrade to rev >= 3\n", si->rev));
95 sd_err(("Attaching to Generic PCI SPI Host Controller Rev %d\n", si->rev));
98 ASSERT(si->rev >= 3);
102 /* Rev < 10 PciSpiHost has 2 BARs:
106 * Rev 10 and up use a different PCI core which only has a single
109 if (si->rev < 10) {
150 if (si->rev >= 4) {
257 /* For FPGA Rev >= 5, the use of an external clock oscillator is supported.
261 if (si->rev >= 5) {
363 /* For Rev 8, writing to the PLL_CTRL register resets
365 * Rev 7 and older, we use a software delay to allow
368 if (si->rev < 8) {
389 if (si->rev >= 10) {
545 /* Only yield the CPU and wait for interrupt on Rev 8 and newer FPGA images. */
546 yield = ((msglen > 500) && (si->rev >= 8));
617 * The state bits are only implemented in Rev >= 5 FPGA. These
618 * bits are hardwired to 00 for Rev < 5, so this check doesn't cause
