1 #ifndef PCI_H 2 #define PCI_H 3 4 /* 5 ** Support for NE2000 PCI clones added David Monro June 1997 6 ** Generalised for other PCI NICs by Ken Yap July 1997 7 ** 8 ** Most of this is taken from: 9 ** 10 ** /usr/src/linux/drivers/pci/pci.c 11 ** /usr/src/linux/include/linux/pci.h 12 ** /usr/src/linux/arch/i386/bios32.c 13 ** /usr/src/linux/include/linux/bios32.h 14 ** /usr/src/linux/drivers/net/ne.c 15 */ 16 17 /* 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2, or (at 21 * your option) any later version. 22 */ 23 24 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 25 #define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */ 26 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 27 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 28 29 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX 30 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101 31 #define PCIBIOS_FIND_PCI_DEVICE 0xb102 32 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103 33 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106 34 #define PCIBIOS_READ_CONFIG_BYTE 0xb108 35 #define PCIBIOS_READ_CONFIG_WORD 0xb109 36 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a 37 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b 38 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c 39 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d 40 41 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 42 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 43 #define PCI_COMMAND 0x04 /* 16 bits */ 44 45 #define PCI_REVISION 0x08 /* 8 bits */ 46 #define PCI_CLASS_CODE 0x0b /* 8 bits */ 47 #define PCI_SUBCLASS_CODE 0x0a /* 8 bits */ 48 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 49 50 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 51 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */ 52 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */ 53 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 54 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 55 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 56 57 #ifndef PCI_BASE_ADDRESS_IO_MASK 58 #define PCI_BASE_ADDRESS_IO_MASK (~0x03) 59 #endif 60 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 61 #define PCI_ROM_ADDRESS 0x30 /* 32 bits */ 62 #define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, 63 bits 31..11 are address, 64 10..2 are reserved */ 65 66 #define PCI_FUNC(devfn) ((devfn) & 0x07) 67 68 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24)) 69 70 /* PCI signature: "PCI " */ 71 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24)) 72 73 /* PCI service signature: "$PCI" */ 74 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24)) 75 76 union bios32 { 77 struct { 78 unsigned long signature; /* _32_ */ 79 unsigned long entry; /* 32 bit physical address */ 80 unsigned char revision; /* Revision level, 0 */ 81 unsigned char length; /* Length in paragraphs should be 01 */ 82 unsigned char checksum; /* All bytes must add up to zero */ 83 unsigned char reserved[5]; /* Must be zero */ 84 } fields; 85 char chars[16]; 86 }; 87 88 #define KERN_CODE_SEG 0x8 /* This _MUST_ match start.S */ 89 90 /* Stuff for asm */ 91 #define save_flags(x) \ 92 __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */ :"memory") 93 94 #define cli() __asm__ __volatile__ ("cli": : :"memory") 95 96 #define restore_flags(x) \ 97 __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory") 98 99 #define PCI_VENDOR_ID_ADMTEK 0x1317 100 #define PCI_DEVICE_ID_ADMTEK_0985 0x0985 101 #define PCI_VENDOR_ID_REALTEK 0x10ec 102 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 103 #define PCI_DEVICE_ID_REALTEK_8139 0x8139 104 #define PCI_VENDOR_ID_WINBOND2 0x1050 105 #define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 106 #define PCI_DEVICE_ID_WINBOND2_89C840 0x0840 107 #define PCI_VENDOR_ID_COMPEX 0x11f6 108 #define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 109 #define PCI_DEVICE_ID_COMPEX_RL100ATX 0x2011 110 #define PCI_VENDOR_ID_KTI 0x8e2e 111 #define PCI_DEVICE_ID_KTI_ET32P2 0x3000 112 #define PCI_VENDOR_ID_NETVIN 0x4a14 113 #define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 114 #define PCI_VENDOR_ID_HOLTEK 0x12c3 115 #define PCI_DEVICE_ID_HOLTEK_HT80232 0x0058 116 #define PCI_VENDOR_ID_3COM 0x10b7 117 #define PCI_DEVICE_ID_3COM_3C590 0x5900 118 #define PCI_DEVICE_ID_3COM_3C595 0x5950 119 #define PCI_DEVICE_ID_3COM_3C595_1 0x5951 120 #define PCI_DEVICE_ID_3COM_3C595_2 0x5952 121 #define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 122 #define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 123 #define PCI_DEVICE_ID_3COM_3C905TX 0x9050 124 #define PCI_DEVICE_ID_3COM_3C905T4 0x9051 125 #define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 126 #define PCI_DEVICE_ID_3COM_3C905C_TXM 0x9200 127 #define PCI_VENDOR_ID_INTEL 0x8086 128 #define PCI_DEVICE_ID_INTEL_82557 0x1229 129 #define PCI_DEVICE_ID_INTEL_82559ER 0x1209 130 #define PCI_DEVICE_ID_INTEL_ID1029 0x1029 131 #define PCI_DEVICE_ID_INTEL_ID1030 0x1030 132 #define PCI_DEVICE_ID_INTEL_82562 0x2449 133 #define PCI_VENDOR_ID_AMD 0x1022 134 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 135 #define PCI_VENDOR_ID_AMD_HOMEPNA 0x1022 136 #define PCI_DEVICE_ID_AMD_HOMEPNA 0x2001 137 #define PCI_VENDOR_ID_SMC_1211 0x1113 138 #define PCI_DEVICE_ID_SMC_1211 0x1211 139 #define PCI_VENDOR_ID_DEC 0x1011 140 #define PCI_DEVICE_ID_DEC_TULIP 0x0002 141 #define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 142 #define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 143 #define PCI_DEVICE_ID_DEC_21142 0x0019 144 #define PCI_VENDOR_ID_SMC 0x10B8 145 #ifndef PCI_DEVICE_ID_SMC_EPIC100 146 # define PCI_DEVICE_ID_SMC_EPIC100 0x0005 147 #endif 148 #define PCI_VENDOR_ID_MACRONIX 0x10d9 149 #define PCI_DEVICE_ID_MX987x5 0x0531 150 #define PCI_VENDOR_ID_LINKSYS 0x11AD 151 #define PCI_DEVICE_ID_LC82C115 0xC115 152 #define PCI_VENDOR_ID_VIATEC 0x1106 153 #define PCI_DEVICE_ID_VIA_RHINE_I 0x3043 154 #define PCI_DEVICE_ID_VIA_VT6102 0x3065 155 #define PCI_DEVICE_ID_VIA_86C100A 0x6100 156 #define PCI_VENDOR_ID_DAVICOM 0x1282 157 #define PCI_DEVICE_ID_DM9009 0x9009 158 #define PCI_DEVICE_ID_DM9102 0x9102 159 #define PCI_VENDOR_ID_SIS 0x1039 160 #define PCI_DEVICE_ID_SIS900 0x0900 161 #define PCI_DEVICE_ID_SIS7016 0x7016 162 #define PCI_VENDOR_ID_DLINK 0x1186 163 #define PCI_DEVICE_ID_DFE530TXP 0x1300 164 #define PCI_VENDOR_ID_NS 0x100B 165 #define PCI_DEVICE_ID_DP83815 0x0020 166 #define PCI_VENDOR_ID_OLICOM 0x108d 167 #define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 168 #define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 169 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 170 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 171 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 172 #define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 173 174 struct pci_device { 175 unsigned short vendor, dev_id; 176 const char *name; 177 unsigned int membase; 178 unsigned short ioaddr; 179 unsigned char devfn; 180 unsigned char bus; 181 }; 182 183 extern void eth_pci_init(struct pci_device *); 184 185 extern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned char *value); 186 extern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, unsigned char value); 187 extern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned short *value); 188 extern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, unsigned short value); 189 extern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned int *value); 190 extern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned int value); 191 void adjust_pci_device(struct pci_device *p); 192 #endif /* PCI_H */ 193
