1 /* 2 * BCM47XX Sonics SiliconBackplane embedded ram core 3 * 4 * Copyright (C) 1999-2010, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * $Id: sbsocram.h,v 13.9.162.2 2008/12/12 14:13:27 Exp $ 25 */ 26 27 28 #ifndef _SBSOCRAM_H 29 #define _SBSOCRAM_H 30 31 #ifndef _LANGUAGE_ASSEMBLY 32 33 34 #ifndef PAD 35 #define _PADLINE(line) pad ## line 36 #define _XSTR(line) _PADLINE(line) 37 #define PAD _XSTR(__LINE__) 38 #endif 39 40 41 typedef volatile struct sbsocramregs { 42 uint32 coreinfo; 43 uint32 bwalloc; 44 uint32 extracoreinfo; 45 uint32 biststat; 46 uint32 bankidx; 47 uint32 standbyctrl; 48 49 uint32 errlogstatus; 50 uint32 errlogaddr; 51 52 uint32 cambankidx; 53 uint32 cambankstandbyctrl; 54 uint32 cambankpatchctrl; 55 uint32 cambankpatchtblbaseaddr; 56 uint32 cambankcmdreg; 57 uint32 cambankdatareg; 58 uint32 cambankmaskreg; 59 uint32 PAD[17]; 60 uint32 extmemconfig; 61 uint32 extmemparitycsr; 62 uint32 extmemparityerrdata; 63 uint32 extmemparityerrcnt; 64 uint32 extmemwrctrlandsize; 65 uint32 PAD[84]; 66 uint32 workaround; 67 uint32 pwrctl; 68 } sbsocramregs_t; 69 70 #endif 71 72 73 #define SR_COREINFO 0x00 74 #define SR_BWALLOC 0x04 75 #define SR_BISTSTAT 0x0c 76 #define SR_BANKINDEX 0x10 77 #define SR_BANKSTBYCTL 0x14 78 #define SR_PWRCTL 0x1e8 79 80 81 #define SRCI_PT_MASK 0x00070000 82 #define SRCI_PT_SHIFT 16 83 84 #define SRCI_PT_OCP_OCP 0 85 #define SRCI_PT_AXI_OCP 1 86 #define SRCI_PT_ARM7AHB_OCP 2 87 #define SRCI_PT_CM3AHB_OCP 3 88 #define SRCI_PT_AXI_AXI 4 89 #define SRCI_PT_AHB_AXI 5 90 91 #define SRCI_LSS_MASK 0x00f00000 92 #define SRCI_LSS_SHIFT 20 93 #define SRCI_LRS_MASK 0x0f000000 94 #define SRCI_LRS_SHIFT 24 95 96 97 #define SRCI_MS0_MASK 0xf 98 #define SR_MS0_BASE 16 99 100 101 #define SRCI_ROMNB_MASK 0xf000 102 #define SRCI_ROMNB_SHIFT 12 103 #define SRCI_ROMBSZ_MASK 0xf00 104 #define SRCI_ROMBSZ_SHIFT 8 105 #define SRCI_SRNB_MASK 0xf0 106 #define SRCI_SRNB_SHIFT 4 107 #define SRCI_SRBSZ_MASK 0xf 108 #define SRCI_SRBSZ_SHIFT 0 109 110 #define SR_BSZ_BASE 14 111 112 113 #define SRSC_SBYOVR_MASK 0x80000000 114 #define SRSC_SBYOVR_SHIFT 31 115 #define SRSC_SBYOVRVAL_MASK 0x60000000 116 #define SRSC_SBYOVRVAL_SHIFT 29 117 #define SRSC_SBYEN_MASK 0x01000000 118 #define SRSC_SBYEN_SHIFT 24 119 120 121 #define SRPC_PMU_STBYDIS_MASK 0x00000010 122 #define SRPC_PMU_STBYDIS_SHIFT 4 123 #define SRPC_STBYOVRVAL_MASK 0x00000008 124 #define SRPC_STBYOVRVAL_SHIFT 3 125 #define SRPC_STBYOVR_MASK 0x00000007 126 #define SRPC_STBYOVR_SHIFT 0 127 128 129 #define SRECC_NUM_BANKS_MASK 0x000000F0 130 #define SRECC_NUM_BANKS_SHIFT 4 131 #define SRECC_BANKSIZE_MASK 0x0000000F 132 #define SRECC_BANKSIZE_SHIFT 0 133 134 #define SRECC_BANKSIZE(value) (1 << (value)) 135 136 137 #define SRCBPC_PATCHENABLE 0x80000000 138 139 #define SRP_ADDRESS 0x0001FFFC 140 #define SRP_VALID 0x8000 141 142 143 #define SRCMD_WRITE 0x00020000 144 #define SRCMD_READ 0x00010000 145 #define SRCMD_DONE 0x80000000 146 147 #define SRCMD_DONE_DLY 1000 148 149 150 #endif 151
