1 /**************************************************************************** 2 **+-----------------------------------------------------------------------+** 3 **| |** 4 **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |** 5 **| All rights reserved. |** 6 **| |** 7 **| Redistribution and use in source and binary forms, with or without |** 8 **| modification, are permitted provided that the following conditions |** 9 **| are met: |** 10 **| |** 11 **| * Redistributions of source code must retain the above copyright |** 12 **| notice, this list of conditions and the following disclaimer. |** 13 **| * Redistributions in binary form must reproduce the above copyright |** 14 **| notice, this list of conditions and the following disclaimer in |** 15 **| the documentation and/or other materials provided with the |** 16 **| distribution. |** 17 **| * Neither the name Texas Instruments nor the names of its |** 18 **| contributors may be used to endorse or promote products derived |** 19 **| from this software without specific prior written permission. |** 20 **| |** 21 **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |** 22 **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |** 23 **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |** 24 **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |** 25 **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |** 26 **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |** 27 **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |** 28 **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |** 29 **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |** 30 **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |** 31 **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |** 32 **| |** 33 **+-----------------------------------------------------------------------+** 34 ****************************************************************************/ 35 36 /**************************************************************************** 37 * 38 * MODULE: ShmFwCtrl.c 39 * PURPOSE: shared memory firmware control 40 * 41 ****************************************************************************/ 42 #include "whalCommon.h" 43 #include "whalBus_Api.h" 44 #include "shmBus.h" 45 #include "TNETWIF.h" 46 #include "whalHwAccess.h" 47 #include "whalHwCtrl.h" 48 #include "shmFwCtrl.h" 49 #include "TNETW_Driver.h" 50 #include "CmdMBox_api.h" 51 #include "eventMbox_api.h" 52 #include "FwEvent_api.h" 53 54 55 /* Firmware image header size */ 56 #define FW_HDR_SIZE 8 57 58 59 static TI_STATUS whal_FwCtrl_BootSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status); 60 static TI_STATUS whal_FwCtrl_ResetSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status); 61 static TI_STATUS whal_FwCtrl_EepromlessStartBurstSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status); 62 static TI_STATUS whal_FwCtrl_InitSequenceSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status); 63 static TI_STATUS whal_FwCtrl_LoadFwImageSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status); 64 static TI_STATUS whal_FwCtrl_FinalizeDownloadSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status); 65 #ifdef USE_SYNC_API 66 static int whal_FwCtrl_Reset (TI_HANDLE hWhalBus); 67 #endif 68 69 70 /* Handle return status inside a state machine */ 71 #define EXCEPT(pwhalbus,status) \ 72 switch (status) { \ 73 case OK: \ 74 case TNETWIF_COMPLETE: \ 75 break; \ 76 case TNETWIF_PENDING: \ 77 return TNETWIF_PENDING; \ 78 default: \ 79 whal_hwCtrl_FinalizeOnFailure (pwhalbus->hHwCtrl); \ 80 return TNETWIF_ERROR; \ 81 } 82 83 84 /* Handle return status inside an init sequence state machine */ 85 #define EXCEPT_I(pwhalbus,status) \ 86 switch (status) { \ 87 case OK: \ 88 case TNETWIF_COMPLETE: \ 89 break; \ 90 case TNETWIF_PENDING: \ 91 pwhalbus->uInitSeqStatus = status; \ 92 return TNETWIF_PENDING; \ 93 default: \ 94 whal_hwCtrl_FinalizeOnFailure (pwhalbus->hHwCtrl); \ 95 return TNETWIF_ERROR; \ 96 } 97 98 99 /* Handle return status inside a load image state machine */ 100 #define EXCEPT_L(pwhalbus,status) \ 101 switch (status) { \ 102 case OK: \ 103 case TNETWIF_COMPLETE: \ 104 break; \ 105 case TNETWIF_PENDING: \ 106 pwhalbus->DownloadStatus = status; \ 107 return TNETWIF_PENDING; \ 108 default: \ 109 pwhalbus->DownloadStatus = status; \ 110 whal_hwCtrl_FinalizeOnFailure (pwhalbus->hHwCtrl); \ 111 return TNETWIF_ERROR; \ 112 } 113 114 115 /**************************************************************************** 116 * whalBus_FwCtrl_Boot() 117 **************************************************************************** 118 * DESCRIPTION: Download firmware code to the Hardware and run it 119 * 120 * INPUTS: None 121 * 122 * OUTPUT: None 123 * 124 * RETURNS: OK or NOK 125 ****************************************************************************/ 126 TI_STATUS whalBus_FwCtrl_Boot (TI_HANDLE hWhalBus, TI_HANDLE hHwCtrl, BootAttr_T *pBootAttr) 127 { 128 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 129 HwCtrl_T *pHwCtrl = (HwCtrl_T *)hHwCtrl; 130 131 pWhalBus->hHwCtrl = hHwCtrl; 132 133 /* Store the pointer to the FW buffer for further use in FW download in part */ 134 pWhalBus->pFwBuf = (UINT8 *)pHwCtrl->uFwBuf; 135 pWhalBus->uFwLastAddr = pHwCtrl->uFwAddr; 136 pWhalBus->pEEPROMBuf = (UINT8 *)pHwCtrl->uEEEPROMBuf; 137 pWhalBus->uEEPROMLen = pHwCtrl->uEEEPROMLen; 138 139 /* 140 * Initialize the status of download to pending 141 * It will be set to TNETWIF_COMPLETE at the FinalizeDownload function 142 */ 143 pWhalBus->DownloadStatus = TNETWIF_PENDING; 144 145 /* Call the boot sequence state machine */ 146 pWhalBus->uInitStage = 0; 147 148 os_memoryCopy (pWhalBus->hOs, &pWhalBus->BootAttr, pBootAttr, sizeof(BootAttr_T)); 149 150 whal_FwCtrl_BootSm (hWhalBus, HAL_INIT_MODULE_ID, OK); 151 152 /* 153 * If it returns the status of the StartInstance only then we can here query for the download status 154 * and then return the status up to the TNETW_Driver. 155 * This return value will go back up to the TNETW Driver layer so that the init from OS will know 156 * if to wait for the InitComplte or not in case of TNETWIF_ERROR. 157 * This value will always be pending since the SPI is ASYNC 158 * and in SDIOa timer is set so it will be ASync also in anyway. 159 */ 160 return pWhalBus->DownloadStatus; 161 } 162 163 164 /**************************************************************************** 165 * DESCRIPTION: Firmware boot state machine 166 * 167 * INPUTS: 168 * TI_HANDLE hWhalBus Handle to the Bus 169 * UINT8 module_id The module id of the Init process in the TNETWIF 170 * 171 * OUTPUT: None 172 * 173 * RETURNS: OK 174 ****************************************************************************/ 175 static TI_STATUS whal_FwCtrl_BootSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status) 176 { 177 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 178 BootAttr_T *pBootAttr; 179 UINT8 minorMinorE2Ver = 0; 180 181 EXCEPT (pWhalBus, status) 182 183 switch (pWhalBus->uInitStage) 184 { 185 case 0: 186 pWhalBus->uInitStage ++; 187 188 pWhalBus->uChipId = 0; 189 190 /* Read the CHIP ID to get an indication that the bus is OK */ 191 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 192 CHIP_ID, 193 &pWhalBus->uChipId, 194 module_id, 195 (TNETWIF_callback_t)whal_FwCtrl_BootSm, 196 hWhalBus); 197 EXCEPT (pWhalBus, status) 198 199 case 1: 200 pWhalBus->uInitStage ++; 201 202 /* This is only sanity check that the HW exists, we can continue and fail on FwLoad */ 203 if (pWhalBus->uChipId == CHIP_ID_1251_PG10) 204 { 205 WLAN_OS_REPORT(("Working on a 1251 PG 1.0 board.\n")); 206 } 207 else if (pWhalBus->uChipId == CHIP_ID_1251_PG11) 208 { 209 WLAN_OS_REPORT(("Working on a 1251 PG 1.1 board.\n")); 210 } 211 else if (pWhalBus->uChipId == CHIP_ID_1251_PG12) 212 { 213 WLAN_OS_REPORT(("Working on a 1251 PG 1.2 board.\n")); 214 } 215 else 216 { 217 WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 218 ("whalBus_FwCtrl_Boot: ERROR, Fail to identify Wlan Hardware card, ChipId(0x%x)=0x%x\n", 219 CHIP_ID, pWhalBus->uChipId)); 220 221 WLAN_OS_REPORT (("Found unknown Chip Id = 0x%x\n", pWhalBus->uChipId)); 222 223 /* 224 * NOTE: no exception because of forward compatibility 225 */ 226 } 227 228 /* 229 * Soft reset 230 */ 231 pWhalBus->uResetStage = 0; 232 pWhalBus->uSelfClearTime = 0; 233 pWhalBus->uBootData = 0; 234 status = whal_FwCtrl_ResetSm (pWhalBus, module_id, OK); 235 236 EXCEPT (pWhalBus, status) 237 238 case 2: 239 pWhalBus->uInitStage ++; 240 241 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("TNET SOFT-RESET\n")); 242 243 WLAN_OS_REPORT(("Starting to process NVS...\n")); 244 245 /* 246 * Start EEPROM/NVS burst (get RadioType) 247 */ 248 if (pWhalBus->pEEPROMBuf) 249 { 250 /* NVS file exists (EEPROM-less support) */ 251 pWhalBus->uEEPROMCurLen = pWhalBus->uEEPROMLen; 252 pWhalBus->pEEPROMCurPtr = pWhalBus->pEEPROMBuf; 253 pWhalBus->uEEPROMStage = 0; 254 255 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 256 ("whal_FwCtrl_EepromlessStartBurst: EEPROM Image addr=0x%x, EEPROM Len=0x0x%x\n", 257 pWhalBus->pEEPROMBuf, pWhalBus->uEEPROMLen)); 258 status = whal_FwCtrl_EepromlessStartBurstSm (hWhalBus, module_id, OK); 259 260 EXCEPT (pWhalBus, status) 261 } 262 263 case 3: 264 pWhalBus->uInitStage ++; 265 266 if (pWhalBus->pEEPROMBuf) 267 { 268 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 269 ACX_EEPROMLESS_IND_REG, 270 pWhalBus->uFwLastAddr, 271 module_id, 272 (TNETWIF_callback_t)whal_FwCtrl_BootSm, 273 hWhalBus); 274 EXCEPT (pWhalBus, status) 275 } 276 277 case 4: 278 pWhalBus->uInitStage ++; 279 280 if (pWhalBus->pEEPROMBuf) 281 { 282 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 283 ("DRIVER NVS BURST-READ\n")); 284 } 285 286 if (!pWhalBus->pEEPROMBuf) 287 { 288 /* 289 * Start ACX EEPROM 290 */ 291 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 292 ACX_REG_EE_START, 293 START_EEPROM_MGR, 294 module_id, 295 (TNETWIF_callback_t)whal_FwCtrl_BootSm, 296 hWhalBus); 297 EXCEPT (pWhalBus, status) 298 } 299 300 case 5: 301 pWhalBus->uInitStage ++; 302 303 if (!pWhalBus->pEEPROMBuf) 304 { 305 /* 306 * The stall is needed so the EEPROM NVS burst read will complete 307 */ 308 os_StalluSec (pWhalBus->hOs, 40000); 309 310 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 311 ACX_EEPROMLESS_IND_REG, 312 USE_EEPROM, 313 module_id, 314 (TNETWIF_callback_t)whal_FwCtrl_BootSm, 315 hWhalBus); 316 EXCEPT (pWhalBus, status) 317 } 318 319 case 6: 320 pWhalBus->uInitStage ++; 321 322 if (!pWhalBus->pEEPROMBuf) 323 { 324 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 325 ("STARTING EEPROM NVS BURST-READ\n")); 326 } 327 328 /* Read the EEPROM parameters */ 329 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 330 SCR_PAD2, 331 &pWhalBus->uBootData, 332 module_id, 333 (TNETWIF_callback_t)whal_FwCtrl_BootSm, 334 hWhalBus); 335 EXCEPT (pWhalBus, status) 336 337 case 7: 338 pWhalBus->uInitStage ++; 339 340 pBootAttr = &pWhalBus->BootAttr; 341 pBootAttr->radioType = (pWhalBus->uBootData & 0x0000FF00) >> 8; 342 pBootAttr->majorE2Ver = (pWhalBus->uBootData & 0x00FF0000) >> 16; 343 344 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 345 SCR_PAD3, 346 &pWhalBus->uBootData, 347 module_id, 348 (TNETWIF_callback_t)whal_FwCtrl_BootSm, 349 hWhalBus); 350 EXCEPT (pWhalBus, status) 351 352 case 8: 353 pWhalBus->uInitStage ++; 354 355 pBootAttr = &pWhalBus->BootAttr; 356 pBootAttr->minorE2Ver = (pWhalBus->uBootData & 0x00FF0000) >> 16; 357 minorMinorE2Ver = (pWhalBus->uBootData & 0xFF000000) >> 24; 358 359 if (pBootAttr->radioType == 0xffffffff) 360 { 361 WLAN_REPORT_FATAL_ERROR (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 362 ("whalBus_FwCtrl_Boot: error in RadioType\n")); 363 EXCEPT (pWhalBus, TNETWIF_ERROR) 364 } 365 366 WLAN_OS_REPORT(("NVS version %d.%d.%d found.\n", pBootAttr->majorE2Ver, pBootAttr->minorE2Ver, minorMinorE2Ver)); 367 WLAN_OS_REPORT(("Radio type is 0x%X.\n", pBootAttr->radioType)); 368 369 /* Call the restart sequence */ 370 pWhalBus->uInitSeqStage = 0; 371 pWhalBus->uInitSeqStatus = TNETWIF_COMPLETE; 372 status = whal_FwCtrl_InitSequenceSm (hWhalBus, module_id, OK); 373 374 EXCEPT (pWhalBus, status) 375 376 case 9: 377 pWhalBus->uInitStage ++; 378 379 WLAN_OS_REPORT(("Finished processing NVS.\n")); 380 381 /* Download the firmware */ 382 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 383 ACX_REG_ECPU_CONTROL, 384 &pWhalBus->uBootData, 385 module_id, 386 (TNETWIF_callback_t)whal_FwCtrl_BootSm, 387 hWhalBus); 388 EXCEPT (pWhalBus, status) 389 390 case 10: 391 pWhalBus->uInitStage = 0; 392 393 if (pWhalBus->pFwBuf && (pWhalBus->uBootData & ECPU_CONTROL_HALT) != 0) 394 { 395 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 396 ("CPU halt -> download code")); 397 398 /* Load firmware image */ 399 pWhalBus->uLoadStage = 0; 400 status = whal_FwCtrl_LoadFwImageSm (pWhalBus, module_id, OK); 401 402 switch (status) 403 { 404 case TNETWIF_COMPLETE: 405 /*WLAN_OS_REPORT (("Firmware successfully downloaded.\n"));*/ 406 break; 407 case TNETWIF_PENDING: 408 WLAN_OS_REPORT (("Starting to download firmware...\n")); 409 break; 410 default: 411 WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, ("Firmware download failed!\n")); 412 break; 413 } 414 415 EXCEPT (pWhalBus, status); 416 } 417 else 418 { 419 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("Firmware not downloaded...\n")); 420 421 EXCEPT (pWhalBus, TNETWIF_ERROR) 422 } 423 424 } /* Switch end */ 425 426 return TNETWIF_COMPLETE; 427 } 428 429 430 /**************************************************************************** 431 * whal_FwCtrl_FinalizeDownloadSm() 432 **************************************************************************** 433 * DESCRIPTION: Run the Hardware firmware 434 * Wait for Init Complete 435 * Configure the Bus Access with Addresses available on the scratch pad register 436 * Change the SDIO/SPI partitions to be able to see all the memory addresses 437 * 438 * INPUTS: None 439 * 440 * OUTPUT: None 441 * 442 * RETURNS: None 443 ****************************************************************************/ 444 static TI_STATUS whal_FwCtrl_FinalizeDownloadSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status) 445 { 446 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 447 448 #define FIN_LOOP 20000 449 450 EXCEPT (pWhalBus, status) 451 452 while (TRUE) 453 { 454 switch (pWhalBus->uFinStage) 455 { 456 case 0: 457 pWhalBus->uFinStage ++; 458 459 /* 460 * Run the firmware (I) 461 */ 462 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 463 ACX_REG_ECPU_CONTROL, 464 &pWhalBus->uFinData, 465 module_id, 466 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 467 hWhalBus); 468 EXCEPT (pWhalBus, status); 469 470 case 1: 471 pWhalBus->uFinStage ++; 472 473 /* 474 * Run the firmware (II) 475 */ 476 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 477 ACX_REG_ECPU_CONTROL, 478 pWhalBus->uFinData & ~ECPU_CONTROL_HALT, 479 module_id, 480 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 481 hWhalBus); 482 EXCEPT (pWhalBus, status); 483 484 case 2: 485 pWhalBus->uFinStage ++; 486 487 #if defined(TNETW1150) && defined(RIVENDELL) 488 /* (!!!1150) added when testing with the prateekai/rivendell */ 489 WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 490 ("whal_hwCtrl_Run: Only 1150 - wait 500 msec between FW download and run CPU\n")); 491 os_StalluSec (pWhalBus->hOs, 500000); 492 #endif 493 494 WLAN_OS_REPORT (("Firmware running.\n")); 495 496 /* 497 * CHIP ID Debug 498 */ 499 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 500 CHIP_ID, 501 &pWhalBus->uFinData, 502 module_id, 503 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 504 hWhalBus); 505 EXCEPT (pWhalBus, status); 506 507 case 3: 508 pWhalBus->uFinStage ++; 509 pWhalBus->uFinLoop = 0; 510 511 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 512 ("CHIP ID IS %x\n", pWhalBus->uFinData)); 513 514 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, ("Wait init complete\n")); 515 516 case 4: 517 /* 518 * Wait for init complete 519 */ 520 if (pWhalBus->uFinLoop < FIN_LOOP) 521 { 522 pWhalBus->uFinStage = 5; 523 524 os_StalluSec (pWhalBus->hOs, 50); 525 526 /* Read interrupt status register */ 527 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 528 ACX_REG_INTERRUPT_NO_CLEAR, 529 &pWhalBus->uFinData, 530 module_id, 531 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 532 hWhalBus); 533 EXCEPT (pWhalBus, status); 534 } 535 else 536 pWhalBus->uFinStage = 6; 537 continue; 538 539 case 5: 540 if (pWhalBus->uFinData == 0xffffffff) /* error */ 541 { 542 WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 543 ("Error reading hardware complete init indication\n")); 544 545 pWhalBus->DownloadStatus = TNETWIF_ERROR; 546 EXCEPT (pWhalBus, TNETWIF_ERROR); 547 } 548 549 if (IS_MASK_ON (pWhalBus->uFinData, ACX_INTR_INIT_COMPLETE)) 550 { 551 pWhalBus->uFinStage = 6; 552 553 /* Interrupt ACK */ 554 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 555 ACX_REG_INTERRUPT_ACK, 556 ACX_INTR_INIT_COMPLETE, 557 module_id, 558 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 559 hWhalBus); 560 EXCEPT (pWhalBus, status); 561 } 562 else 563 { 564 pWhalBus->uFinStage = 4; 565 pWhalBus->uFinLoop ++; 566 } 567 continue; 568 569 case 6: 570 pWhalBus->uFinStage = 7; 571 572 if (pWhalBus->uFinLoop >= FIN_LOOP) 573 { 574 WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 575 ("Timeout waiting for the hardware to complete initialization\n")); 576 577 pWhalBus->DownloadStatus = TNETWIF_ERROR; 578 EXCEPT (pWhalBus, TNETWIF_ERROR); 579 } 580 581 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("Firmware init complete...\n")); 582 583 /* 584 * There are valid addresses of the command and event mailbox 585 * on the scratch pad registers 586 */ 587 { 588 /* Hardware config command mail box */ 589 TnetwDrv_t *pTnetwDrv = (TnetwDrv_t *)pWhalBus->hTnetwDrv; 590 status = CmdMBox_ConfigHw (pTnetwDrv->hCmdMBox, 591 module_id, 592 (fnotify_t)whal_FwCtrl_FinalizeDownloadSm, 593 hWhalBus); 594 EXCEPT (pWhalBus, status); 595 } 596 continue; 597 598 case 7: 599 pWhalBus->uFinStage = 8; 600 601 { 602 /* Hardware config event mail box */ 603 TnetwDrv_t *pTnetwDrv = (TnetwDrv_t *)pWhalBus->hTnetwDrv; 604 status = eventMbox_ConfigHw (pTnetwDrv->hEventMbox, 605 module_id, 606 (fnotify_t)whal_FwCtrl_FinalizeDownloadSm, 607 hWhalBus); 608 EXCEPT (pWhalBus, status); 609 } 610 continue; 611 612 case 8: 613 pWhalBus->uFinStage = 9; 614 615 /* Set the working partition to its "running" mode offset */ 616 #if defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI) 617 status = TNETWIF_SetPartitionsOpt (pWhalBus->hTNETWIF, 618 HW_ACCESS_WORKING, 619 HW_ACCESS_WORK_PART0_ADDR, 620 module_id, 621 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 622 hWhalBus); 623 EXCEPT (pWhalBus, status); 624 #endif 625 continue; 626 627 case 9: 628 pWhalBus->uFinStage = 10; 629 630 /* 631 * In case of full asynchronous mode the firmware event must be ready 632 * to receive event from the command mailbox 633 */ 634 { 635 TnetwDrv_t *pTnetwDrv = (TnetwDrv_t *)pWhalBus->hTnetwDrv; 636 UINT32 uIntVect; 637 638 if (pWhalBus->recoveryProcess == FALSE) 639 FwEvent_Config (pTnetwDrv->hFwEvent, pWhalBus->hTnetwDrv); 640 641 #if !defined(USE_SYNC_API) 642 643 /* This makes command mailbox to work in normal mode */ 644 whalBus_ExitFromInitMode (hWhalBus); 645 646 /* Enable command complete interrupt */ 647 FwEvent_Enable (pTnetwDrv->hFwEvent, ACX_INTR_CMD_COMPLETE); 648 649 /* At the driver init the interrupts must be disabled */ 650 os_enableIrq (pWhalBus->hOs); 651 652 #endif 653 654 #ifdef PRIODIC_INTERRUPT 655 /* Enable periodic interrupts. It means that every period of time the FwEvent SM will be called */ 656 os_periodicIntrTimerStart (pWhalBus->hOs); 657 #endif 658 659 uIntVect = FwEvent_GetEnabled (pTnetwDrv->hFwEvent); 660 661 /* Clearing all the interrupt status register sources */ 662 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 663 ACX_REG_INTERRUPT_MASK, 664 ~uIntVect, 665 module_id, 666 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 667 hWhalBus); 668 } 669 670 EXCEPT (pWhalBus, status); 671 continue; 672 673 case 10: 674 pWhalBus->uFinStage = 11; 675 676 /* 677 * Setting the right operation of the interrupt 678 * bit 5 - enable interrupt 679 * bit 7 - active low 680 */ 681 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 682 HI_CFG, 683 HI_CFG_DEF_VAL, 684 module_id, 685 (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm, 686 hWhalBus); 687 EXCEPT (pWhalBus, status); 688 continue; 689 690 case 11: 691 pWhalBus->uFinStage = 0; 692 693 #ifdef DEBUG_INTERRUPTS_PRINT 694 WLAN_REPORT_INFORMATION (pHwIntr->hReport, 695 HAL_HW_CTRL_MODULE_LOG, 696 ("whal_hwIntr_EnableInterrupts(0x%08X)", 697 pHwIntr->InterruptEnabled)); 698 #endif 699 700 #if defined(HAL_ON_WIN) 701 /* (!!!) Only in CardBus, add HostIfType parameter */ 702 /* Enable interrupt on a CardBus */ 703 TNETWIF_WriteRegSync (pWhalBus->hTNETWIF, FEMR, 0x8000); 704 #endif 705 706 /* 707 * The last thing to be done after the upper layers have been called 708 * is to send FINISH to the TNETWIF to end the init process 709 */ 710 TNETWIF_Finish (pWhalBus->hTNETWIF, HAL_INIT_MODULE_ID, hWhalBus, NULL); 711 712 /* Call the whal_hwCtrl_FinalizeDownload of the upper layer to finalize the download process */ 713 whal_hwCtrl_FinalizeDownload (pWhalBus->hHwCtrl, &pWhalBus->BootAttr); 714 715 /* Set the Download Status to COMPLETE */ 716 pWhalBus->DownloadStatus = TNETWIF_COMPLETE; 717 718 return TNETWIF_COMPLETE; 719 720 } /* End switch */ 721 722 } /* End while */ 723 724 } 725 726 727 #ifdef USE_SYNC_API 728 729 /**************************************************************************** 730 * whal_hwCtrl_Reset() 731 **************************************************************************** 732 * DESCRIPTION: Reset the Hardware 733 * 734 * INPUTS: None 735 * 736 * OUTPUT: None 737 * 738 * RETURNS: OK or NOK 739 ****************************************************************************/ 740 static int whal_FwCtrl_Reset (TI_HANDLE hWhalBus) 741 { 742 #ifdef USE_SYNC_API 743 744 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 745 UINT32 data; 746 747 #ifdef TNETW1251 748 749 /***************************************************************/ 750 /* SOFT RESET is done here - its a temporary fix */ 751 /***************************************************************/ 752 UINT32 SelfClearTime; 753 754 /* 755 * Perform Soft Reset 756 */ 757 TNETWIF_WriteRegSync(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET, SLV_SOFT_RESET_BIT); 758 759 /* SOFT_RESET - Self clearing */ 760 for (SelfClearTime=0; SelfClearTime<SOFT_RESET_MAX_TIME; SelfClearTime+=SOFT_RESET_STALL_TIME) 761 { 762 TNETWIF_ReadRegSync(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET,&data); 763 if (( data & SLV_SOFT_RESET_BIT) == 0) 764 break; 765 os_StalluSec(pWhalBus->hOs, SOFT_RESET_STALL_TIME); 766 } 767 768 WLAN_REPORT_INFORMATION(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 769 ("whal_hwCtrl_Reset: SOFT_RESET Self clearing time = %d (%d)\n", SelfClearTime, SOFT_RESET_MAX_TIME)); 770 if (SelfClearTime >= SOFT_RESET_MAX_TIME) 771 { 772 WLAN_REPORT_FATAL_ERROR(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 773 ("whal_hwCtrl_Reset: ACX_REG_SLV_SOFT_RESET - Self clearing timer expired !!!\n")); 774 return NOK; 775 } 776 777 /***************************************************************/ 778 /* SOFT RESET is done here - its a temporary fix */ 779 /***************************************************************/ 780 781 /* Disable Rx/Tx */ 782 TNETWIF_WriteRegSync(pWhalBus->hTNETWIF, ENABLE, 0x0); /* disable TX,RX */ 783 784 /* Auto Calibration on start Disable */ 785 TNETWIF_WriteRegSync(pWhalBus->hTNETWIF, SPARE_A2, (UINT32)0xFFFF); 786 787 #else /* TNETW1251 */ 788 UINT32 SelfClearTime; 789 790 /* 791 * Halt the Acx Cpu 792 */ 793 TNETWIF_RegIsBitSet(pWhalBus->hTNETWIF, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT); 794 795 /* 796 * Reset the ACX cpu 797 */ 798 TNETWIF_RegIsBitSet(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET, SLV_SOFT_RESET_BIT); 799 800 /* 801 * Wait for Soft reset (Self clearing only in 1150) 802 */ 803 #if defined(TNETW1150) 804 /* SOFT_RESET - Self clearing only on 1150 */ 805 for (SelfClearTime=0; SelfClearTime<SOFT_RESET_MAX_TIME; SelfClearTime+=SOFT_RESET_STALL_TIME) 806 { 807 os_StalluSec(pWhalBus->hOs, SOFT_RESET_STALL_TIME); 808 809 if (((TNETWIF_ReadRegSync(pWhalBus->hTNETWIF,ACX_REG_SLV_SOFT_RESET,&data)) & SLV_SOFT_RESET_BIT) == 0) 810 break; 811 } 812 813 WLAN_REPORT_INFORMATION(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 814 ("whal_hwCtrl_Reset: SOFT_RESET Self clearing time = %d (%d)\n", SelfClearTime, SOFT_RESET_MAX_TIME)); 815 if (SelfClearTime >= SOFT_RESET_MAX_TIME) 816 { 817 WLAN_REPORT_FATAL_ERROR(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 818 ("whal_hwCtrl_Reset: ACX_REG_SLV_SOFT_RESET - Self clearing timer expired !!!\n")); 819 return NOK; 820 } 821 #else 822 os_StalluSec(pWhalBus->hOs, 10000); 823 TNETWIF_RegResetBitVal(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET, SLV_SOFT_RESET_BIT); 824 #endif 825 826 /* 827 * Start Acx Eeprom 828 */ 829 TNETWIF_RegIsBitSet(pWhalBus->hTNETWIF, ACX_REG_EE_START, START_EEPROM_MGR); 830 831 /* Do Not Reduce the StallSec time !!!!! */ 832 os_StalluSec(pWhalBus->hOs, 40000); 833 834 #endif /* TNETW1251 */ 835 836 #endif /* USE_SYNC_API*/ 837 838 return OK; 839 } 840 841 #endif /* USE_SYNC_API */ 842 843 844 /**************************************************************************** 845 * whal_hwCtrl_Reset() 846 **************************************************************************** 847 * DESCRIPTION: Reset hardware state machine 848 * 849 * INPUTS: None 850 * 851 * OUTPUT: None 852 * 853 * RETURNS: OK or NOK 854 ****************************************************************************/ 855 static TI_STATUS whal_FwCtrl_ResetSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status) 856 { 857 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 858 859 /***************************************************************/ 860 /* SOFT RESET is done here - its a temporary fix */ 861 /***************************************************************/ 862 863 EXCEPT (pWhalBus, status); 864 865 switch (pWhalBus->uResetStage) 866 { 867 case 0: 868 /* 869 * Perform soft reset 870 */ 871 pWhalBus->uResetStage ++; 872 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 873 ACX_REG_SLV_SOFT_RESET, 874 SLV_SOFT_RESET_BIT, 875 module_id, 876 (TNETWIF_callback_t)whal_FwCtrl_ResetSm, 877 hWhalBus); 878 EXCEPT (pWhalBus, status); 879 880 case 1: 881 /* SOFT_RESET - self clearing */ 882 while (pWhalBus->uSelfClearTime < SOFT_RESET_MAX_TIME) 883 { 884 if (pWhalBus->uSelfClearTime != 0) 885 { 886 if ((pWhalBus->uBootData & SLV_SOFT_RESET_BIT) == 0) 887 break; 888 os_StalluSec (pWhalBus->hOs, SOFT_RESET_STALL_TIME); 889 } 890 891 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 892 ACX_REG_SLV_SOFT_RESET, 893 &pWhalBus->uBootData, 894 module_id, 895 (TNETWIF_callback_t)whal_FwCtrl_ResetSm, 896 hWhalBus); 897 898 pWhalBus->uSelfClearTime += SOFT_RESET_STALL_TIME; 899 900 EXCEPT (pWhalBus, status); 901 } 902 903 pWhalBus->uResetStage ++; 904 905 case 2: 906 pWhalBus->uResetStage ++; 907 908 WLAN_REPORT_INFORMATION (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 909 ("whal_hwCtrl_Reset: SOFT_RESET self clearing time = %d (%d)\n", 910 pWhalBus->uSelfClearTime, SOFT_RESET_MAX_TIME)); 911 if (pWhalBus->uSelfClearTime >= SOFT_RESET_MAX_TIME) 912 { 913 WLAN_REPORT_FATAL_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 914 ("whal_hwCtrl_Reset: ACX_REG_SLV_SOFT_RESET - Self clearing timer expired !!!\n")); 915 EXCEPT (pWhalBus, TNETWIF_ERROR); 916 } 917 918 case 3: 919 pWhalBus->uResetStage ++; 920 921 /* Disable Rx/Tx */ 922 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 923 ENABLE, 924 0x0, 925 module_id, 926 (TNETWIF_callback_t)whal_FwCtrl_ResetSm, 927 hWhalBus); 928 EXCEPT (pWhalBus, status); 929 930 case 4: 931 pWhalBus->uResetStage ++; 932 933 /* Disable auto calibration on start */ 934 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 935 SPARE_A2, 936 0xFFFF, 937 module_id, 938 (TNETWIF_callback_t)whal_FwCtrl_ResetSm, 939 hWhalBus); 940 return status; 941 942 case 5: 943 pWhalBus->uResetStage = 0; 944 945 /* If the previous status was pending call the upper layer init state machine */ 946 whal_FwCtrl_BootSm (hWhalBus, module_id, status); 947 } 948 949 return status; 950 } 951 952 953 /**************************************************************************** 954 * whal_FwCtrl_Eepromless_StartBurst() 955 **************************************************************************** 956 * DESCRIPTION: prepare eepromless configuration before boot 957 * 958 * INPUTS: 959 * 960 * OUTPUT: 961 * 962 * RETURNS: 963 ****************************************************************************/ 964 static TI_STATUS whal_FwCtrl_EepromlessStartBurstSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status) 965 { 966 whalBus_T* pWhalBus = (whalBus_T *)hWhalBus; 967 968 EXCEPT (pWhalBus, status); 969 970 while (TRUE) 971 { 972 switch (pWhalBus->uEEPROMStage) 973 { 974 case 0: 975 if ((pWhalBus->uEEPROMRegAddr = pWhalBus->pEEPROMCurPtr[1]) & 1) 976 { 977 pWhalBus->uEEPROMRegAddr &= 0xfe; 978 pWhalBus->uEEPROMRegAddr |= (UINT32)pWhalBus->pEEPROMCurPtr[2] << 8; 979 pWhalBus->uEEPROMBurstLen = pWhalBus->pEEPROMCurPtr[0]; 980 pWhalBus->pEEPROMCurPtr += 3; 981 pWhalBus->uEEPROMBurstLoop = 0; 982 pWhalBus->uEEPROMStage = 1; 983 } 984 else 985 { 986 if (pWhalBus->pEEPROMCurPtr[0] == 0) 987 pWhalBus->pEEPROMCurPtr += 7; 988 pWhalBus->uEEPROMCurLen -= pWhalBus->pEEPROMCurPtr - pWhalBus->pEEPROMBuf; 989 pWhalBus->uEEPROMCurLen = (pWhalBus->uEEPROMCurLen + NVS_DATA_BUNDARY_ALIGNMENT - 1) & 0xfffffffc; 990 pWhalBus->uEEPROMStage = 2; 991 } 992 continue; 993 994 case 1: 995 if (pWhalBus->uEEPROMBurstLoop < pWhalBus->uEEPROMBurstLen) 996 { 997 UINT32 val = (pWhalBus->pEEPROMCurPtr[0] | 998 (pWhalBus->pEEPROMCurPtr[1] << 8) | 999 (pWhalBus->pEEPROMCurPtr[2] << 16) | 1000 (pWhalBus->pEEPROMCurPtr[3] << 24)); 1001 1002 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 1003 ("NVS::BurstRead: *(%08x) = %x\n", pWhalBus->uEEPROMRegAddr, val)); 1004 1005 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1006 pWhalBus->uEEPROMRegAddr, 1007 val, 1008 module_id, 1009 (TNETWIF_callback_t)whal_FwCtrl_EepromlessStartBurstSm, 1010 hWhalBus); 1011 1012 pWhalBus->uEEPROMStatus = status; 1013 pWhalBus->uEEPROMRegAddr += 4; 1014 pWhalBus->pEEPROMCurPtr += 4; 1015 pWhalBus->uEEPROMStage = 1; 1016 pWhalBus->uEEPROMBurstLoop ++; 1017 1018 EXCEPT (pWhalBus, status); 1019 } 1020 else 1021 pWhalBus->uEEPROMStage = 0; 1022 continue; 1023 1024 case 2: 1025 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 1026 ("Get NVS file information: NvsDataLen = %#x TableAddr %#x\n", pWhalBus->uEEPROMCurLen, pWhalBus->uFwLastAddr)); 1027 pWhalBus->uNVSStartAddr = pWhalBus->uFwLastAddr; 1028 pWhalBus->uNVSNumChar = 0; 1029 pWhalBus->uNVSNumByte = 0; 1030 pWhalBus->uNVSTempWord = 0; 1031 pWhalBus->uEEPROMStage = 3; 1032 1033 #if defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI) 1034 status = TNETWIF_SetPartitionsOpt (pWhalBus->hTNETWIF, 1035 HW_ACCESS_DOWNLOAD, 1036 pWhalBus->uNVSStartAddr, 1037 module_id, 1038 (TNETWIF_callback_t)whal_FwCtrl_EepromlessStartBurstSm, 1039 hWhalBus); 1040 EXCEPT (pWhalBus, status); 1041 #endif 1042 continue; 1043 1044 case 3: 1045 /* 1046 * Download EEPROM data to ACX internal memory 1047 */ 1048 if (pWhalBus->uNVSNumChar < pWhalBus->uEEPROMCurLen) 1049 { 1050 pWhalBus->uNVSTempWord |= (*pWhalBus->pEEPROMCurPtr) << (8 * pWhalBus->uNVSNumByte); 1051 pWhalBus->pEEPROMCurPtr ++; 1052 pWhalBus->uNVSNumChar ++; 1053 1054 if (++pWhalBus->uNVSNumByte > 3) 1055 { 1056 pWhalBus->uEEPROMStage = 4; 1057 pWhalBus->uNVSTempWord = ENDIAN_HANDLE_LONG (pWhalBus->uNVSTempWord); 1058 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 1059 ("NVS::WriteTable: *(%08x) = %x\n", pWhalBus->uNVSStartAddr, pWhalBus->uNVSTempWord)); 1060 status = TNETWIF_WriteMemOpt (pWhalBus->hTNETWIF, 1061 pWhalBus->uNVSStartAddr, 1062 PADWRITE (&pWhalBus->uNVSTempWord), 1063 sizeof(pWhalBus->uNVSTempWord), 1064 module_id, 1065 (TNETWIF_callback_t)whal_FwCtrl_EepromlessStartBurstSm, 1066 hWhalBus); 1067 pWhalBus->uNVSStatus = status; 1068 1069 EXCEPT (pWhalBus, status); 1070 } 1071 } 1072 else 1073 { 1074 /* Call the upper level state machine */ 1075 if (pWhalBus->uEEPROMStatus == TNETWIF_PENDING || 1076 pWhalBus->uNVSStatus == TNETWIF_PENDING) 1077 whal_FwCtrl_BootSm (hWhalBus, module_id, status); 1078 1079 return TNETWIF_COMPLETE; 1080 } 1081 continue; 1082 1083 case 4: 1084 pWhalBus->uNVSStartAddr += 4; 1085 pWhalBus->uNVSTempWord = 0; 1086 pWhalBus->uNVSNumByte = 0; 1087 pWhalBus->uEEPROMStage = 3; 1088 continue; 1089 1090 } /* End switch */ 1091 1092 } /* End while */ 1093 1094 } 1095 1096 1097 /**************************************************************************** 1098 * whal_FwCtrl_InitSequenceSm() 1099 **************************************************************************** 1100 * DESCRIPTION: the restart wakeup sequence state machine 1101 * 1102 * INPUTS: None 1103 * 1104 * OUTPUT: None 1105 * 1106 * RETURNS: OK or NOK 1107 ****************************************************************************/ 1108 static TI_STATUS whal_FwCtrl_InitSequenceSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status) 1109 { 1110 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 1111 1112 static const UINT32 LUT [REF_FREQ_NUM][LUT_PARAM_NUM] = 1113 { /* INTEGER_DIVIDER FRACTIONAL_DIVIDER ATTN_BB ALPHA_BB STOP_TIME_BB BB_PLL_LOOP_FILTER */ 1114 { 83, 87381, 0xB, 5, 0xF00, 3}, /* REF_FREQ_19_2*/ 1115 { 61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/ 1116 { 41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/ 1117 { 40, 0, 0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/ 1118 { 47, 162280, 0xC, 6, 0x2760, 1} /* REF_FREQ_33_6 */ 1119 }; 1120 1121 EXCEPT_I (pWhalBus, status); 1122 1123 switch (pWhalBus->uInitSeqStage) 1124 { 1125 case 0: 1126 pWhalBus->uInitSeqStage ++; 1127 1128 WLAN_REPORT_INIT(pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("Starting INIT sequence\n")); 1129 1130 /* Read NVS params */ 1131 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 1132 SCR_PAD6, 1133 &pWhalBus->uScrPad6, 1134 module_id, 1135 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1136 hWhalBus); 1137 EXCEPT_I (pWhalBus, status); 1138 1139 case 1: 1140 pWhalBus->uInitSeqStage ++; 1141 /* Read ELP_CMD */ 1142 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 1143 ELP_CMD, 1144 &pWhalBus->uElpCmd, 1145 module_id, 1146 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1147 hWhalBus); 1148 EXCEPT_I (pWhalBus, status); 1149 1150 case 2: 1151 pWhalBus->uInitSeqStage ++; 1152 1153 pWhalBus->uRefFreq = pWhalBus->uScrPad6 & 0x000000FF; 1154 1155 /******************** Set ELP configuration *********************/ 1156 1157 /* 1158 * Set the BB Calibration time to be 300 usec (PLL_CAL_TIME) 1159 */ 1160 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1161 PLL_CAL_TIME/*0x5810*/, 1162 0x9/*0x4*/, 1163 module_id, 1164 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1165 hWhalBus); 1166 EXCEPT_I (pWhalBus, status); 1167 1168 case 3: 1169 pWhalBus->uInitSeqStage ++; 1170 1171 /* PG 1.1 & 1.0: Set the clock buffer time to be 760 usec (CLK_BUF_TIME) */ 1172 if (pWhalBus->uChipId == CHIP_ID_1251_PG10 || 1173 pWhalBus->uChipId == CHIP_ID_1251_PG11) 1174 { 1175 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1176 CLK_BUF_TIME/*0x5818*/, 1177 0x19, 1178 module_id, 1179 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1180 hWhalBus); 1181 } 1182 /* PG 1.2: Set the clock buffer time to be 210 usec (CLK_BUF_TIME) */ 1183 else 1184 { 1185 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1186 CLK_BUF_TIME/*0x5818*/, 1187 0x6, 1188 module_id, 1189 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1190 hWhalBus); 1191 } 1192 EXCEPT_I (pWhalBus, status); 1193 1194 case 4: 1195 pWhalBus->uInitSeqStage ++; 1196 1197 /* 1198 * Set the clock detect feature to work in the restart wu procedure (ELP_CFG_MODE[14]) 1199 * & 1200 * Select the clock source type (ELP_CFG_MODE[13:12] ) 1201 */ 1202 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1203 ELP_CFG_MODE/*0x5804*/, 1204 ((pWhalBus->uScrPad6 & 0x0000FF00) << 4) | 0x00004000, 1205 module_id, 1206 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1207 hWhalBus); 1208 EXCEPT_I (pWhalBus, status); 1209 1210 case 5: 1211 pWhalBus->uInitSeqStage ++; 1212 1213 /* PG 1.1 & 1.0 */ 1214 if (pWhalBus->uChipId == CHIP_ID_1251_PG10 || 1215 pWhalBus->uChipId == CHIP_ID_1251_PG11) 1216 { 1217 /* Do nothing */ 1218 } 1219 1220 /* PG 1.2: Enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */ 1221 else 1222 { 1223 pWhalBus->uElpCmd |= 0x00000040; 1224 1225 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1226 ELP_CMD/*0x5808*/, 1227 pWhalBus->uElpCmd, 1228 module_id, 1229 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1230 hWhalBus); 1231 EXCEPT_I (pWhalBus, status); 1232 } 1233 1234 1235 case 6: 1236 pWhalBus->uInitSeqStage ++; 1237 1238 /* PG 1.1 & 1.0: set the BB PLL stable time to be 30usec (PLL_STABLE_TIME) */ 1239 if (pWhalBus->uChipId == CHIP_ID_1251_PG10 || 1240 pWhalBus->uChipId == CHIP_ID_1251_PG11) 1241 { 1242 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1243 CFG_PLL_SYNC_CNT/*0x5820*/, 1244 0x00, 1245 module_id, 1246 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1247 hWhalBus); 1248 } 1249 1250 /* PG 1.2: Set the BB PLL stable time to be 1000usec (PLL_STABLE_TIME) */ 1251 else 1252 { 1253 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1254 CFG_PLL_SYNC_CNT/*0x5820*/, 1255 0x20, 1256 module_id, 1257 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1258 hWhalBus); 1259 } 1260 1261 EXCEPT_I (pWhalBus, status); 1262 1263 case 7: 1264 pWhalBus->uInitSeqStage ++; 1265 1266 /* PG 1.1 & 1.0 */ 1267 if (pWhalBus->uChipId == CHIP_ID_1251_PG10 || 1268 pWhalBus->uChipId == CHIP_ID_1251_PG11) 1269 { 1270 /* Do nothing */ 1271 } 1272 1273 /* PG 1.2: read clock request time */ 1274 else 1275 { 1276 status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF, 1277 CLK_REQ_TIME/*0x5814*/, 1278 &pWhalBus->uInitData, 1279 module_id, 1280 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1281 hWhalBus); 1282 EXCEPT_I (pWhalBus, status); 1283 } 1284 1285 case 8: 1286 pWhalBus->uInitSeqStage ++; 1287 1288 /* PG 1.1 & 1.0 */ 1289 if (pWhalBus->uChipId == CHIP_ID_1251_PG10 || 1290 pWhalBus->uChipId == CHIP_ID_1251_PG11) 1291 { 1292 /* Do nothing */ 1293 } 1294 1295 /* PG 1.2: set the clock request time to be [ref_clk_settling_time-1mS] 4ms */ 1296 else 1297 { 1298 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 1299 ("CLK_REQ_TIME: read = 0x%x write = 0x%x\n", 1300 pWhalBus->uInitData,((pWhalBus->uInitData > 0x21) ? (pWhalBus->uInitData - 0x21) : 0 ))); 1301 1302 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1303 CLK_REQ_TIME/*0x5814*/, 1304 ((pWhalBus->uInitData > 0x21) ? (pWhalBus->uInitData - 0x21) : 0 ), 1305 module_id, 1306 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1307 hWhalBus); 1308 EXCEPT_I (pWhalBus, status); 1309 } 1310 1311 case 9: 1312 pWhalBus->uInitSeqStage ++; 1313 1314 /******************** Set BB PLL configurations in RF AFE *********************/ 1315 1316 /* 1317 * Set RF_AFE_REG_3 1318 */ 1319 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1320 0x58CC, 1321 0x4B5, 1322 module_id, 1323 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1324 hWhalBus); 1325 EXCEPT_I (pWhalBus, status); 1326 1327 case 10: 1328 pWhalBus->uInitSeqStage ++; 1329 1330 /* 1331 * Set RF_AFE_REG_5 1332 */ 1333 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1334 0x58D4, 1335 0x50/*0x150*/, 1336 module_id, 1337 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1338 hWhalBus); 1339 EXCEPT_I (pWhalBus, status); 1340 1341 case 11: 1342 pWhalBus->uInitSeqStage ++; 1343 1344 /* 1345 * Set RF_AFE_CTRL_REG_2 1346 */ 1347 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1348 0x5948, 1349 0x11C001, 1350 module_id, 1351 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1352 hWhalBus); 1353 EXCEPT_I (pWhalBus, status); 1354 1355 case 12: 1356 pWhalBus->uInitSeqStage ++; 1357 1358 /* 1359 * Change RF PLL and BB PLL divider for VCO clock and adjust VCO bais current(RF_AFE_REG_13) 1360 */ 1361 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1362 0x58F4, 1363 0x1E, 1364 module_id, 1365 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1366 hWhalBus); 1367 EXCEPT_I (pWhalBus, status); 1368 1369 case 13: 1370 pWhalBus->uInitSeqStage ++; 1371 1372 /******************** Set BB PLL configurations *********************/ 1373 1374 /* 1375 * Set integer divider according to Appendix C-BB PLL Calculations. 1376 * & 1377 * Set dither scale to 0. 1378 * & 1379 * Enable complex zero 1380 * & 1381 * Set the location of complex zero 1382 * & 1383 * Set the order of the sigma delta to 2nd order 1384 * & 1385 *Disable the async load 1386 */ 1387 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1388 0x5840, 1389 LUT[pWhalBus->uRefFreq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000, 1390 module_id, 1391 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1392 hWhalBus); 1393 EXCEPT_I (pWhalBus, status); 1394 1395 case 14: 1396 pWhalBus->uInitSeqStage ++; 1397 1398 /* 1399 * Set fractional divider according to Appendix C-BB PLL Calculations 1400 */ 1401 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1402 0x5844, 1403 LUT[pWhalBus->uRefFreq][LUT_PARAM_FRACTIONAL_DIVIDER], 1404 module_id, 1405 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1406 hWhalBus); 1407 EXCEPT_I (pWhalBus, status); 1408 1409 case 15: 1410 pWhalBus->uInitSeqStage ++; 1411 1412 /* 1413 * Set the initial data for the sigma delta 1414 */ 1415 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1416 0x5848, 1417 0x3039, 1418 module_id, 1419 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1420 hWhalBus); 1421 EXCEPT_I (pWhalBus, status); 1422 1423 case 16: 1424 pWhalBus->uInitSeqStage ++; 1425 1426 /* 1427 * Set the accumulator attenuation value 1428 * & 1429 * Set calibration loop1 (alpha) 1430 * & 1431 * Set calibration loop2 (beta) 1432 * & 1433 * Set calibration loop3 (gamma) 1434 * & 1435 * Set the VCO gain 1436 */ 1437 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1438 0x5854, 1439 (LUT[pWhalBus->uRefFreq][LUT_PARAM_ATTN_BB] << 16) | (LUT[pWhalBus->uRefFreq][LUT_PARAM_ALPHA_BB] << 12) | 0x1, 1440 module_id, 1441 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1442 hWhalBus); 1443 EXCEPT_I (pWhalBus, status); 1444 1445 case 17: 1446 pWhalBus->uInitSeqStage ++; 1447 1448 /* 1449 * Set the calibration stop time after holdoff time expires 1450 * & 1451 * Set settling time HOLD_OFF_TIME_BB 1452 */ 1453 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1454 0x5858, 1455 LUT[pWhalBus->uRefFreq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000, 1456 module_id, 1457 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1458 hWhalBus); 1459 EXCEPT_I (pWhalBus, status); 1460 1461 case 18: 1462 pWhalBus->uInitSeqStage ++; 1463 1464 /* 1465 * Set BB PLL Loop filter capacitor3- BB_C3[2:0] 1466 * & 1467 * Set BB PLL constant leakage current to linearize PFD to 0uA- BB_ILOOPF[7:3] 1468 */ 1469 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1470 0x58F8, 1471 LUT[pWhalBus->uRefFreq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030, 1472 module_id, 1473 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1474 hWhalBus); 1475 EXCEPT_I (pWhalBus, status); 1476 1477 case 19: 1478 pWhalBus->uInitSeqStage ++; 1479 1480 /* 1481 * Set regulator output voltage for n divider to 1.35- BB_REFDIV[1:0] 1482 * & 1483 * Set Charge pump current- BB_CPGAIN[4:2] 1484 * & 1485 * Set BB PLL Loop filter capacitor2- BB_C2[7:5] 1486 * & 1487 * Set gain of BB PLL auto-call to normal mode- BB_CALGAIN_3DB[8] 1488 */ 1489 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1490 0x58F0, 1491 0x29, 1492 module_id, 1493 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1494 hWhalBus); 1495 EXCEPT_I (pWhalBus, status); 1496 1497 case 20: 1498 pWhalBus->uInitSeqStage ++; 1499 1500 /******************** Enable restart sequence *********************/ 1501 1502 /* 1503 * Enable restart wakeup sequence (ELP_CMD[0]) 1504 */ 1505 status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF, 1506 ELP_CMD/*0x5808*/, 1507 pWhalBus->uElpCmd | 0x1, 1508 module_id, 1509 (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm, 1510 hWhalBus); 1511 EXCEPT_I (pWhalBus, status); 1512 1513 case 21: 1514 pWhalBus->uInitSeqStage = 0; 1515 1516 os_StalluSec (pWhalBus->hOs, 2000); 1517 1518 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("End INIT sequence\n")); 1519 1520 /* Call upper layer state machine */ 1521 if (pWhalBus->uInitSeqStatus == TNETWIF_PENDING) 1522 whal_FwCtrl_BootSm (hWhalBus, module_id, OK); 1523 1524 } /* End switch */ 1525 1526 return TNETWIF_COMPLETE; 1527 } 1528 1529 1530 /**************************************************************************** 1531 * whal_FwCtrl_LoadFwImageSm() 1532 **************************************************************************** 1533 * DESCRIPTION: Load image from the host and download into the hardware 1534 * 1535 * INPUTS: None 1536 * 1537 * OUTPUT: None 1538 * 1539 * RETURNS: OK or NOK 1540 ****************************************************************************/ 1541 1542 #define ADDR_OFFS HW_ACCESS_DOWN_PART0_ADDR 1543 1544 1545 static TI_STATUS whal_FwCtrl_LoadFwImageSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status) 1546 { 1547 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 1548 1549 EXCEPT_L (pWhalBus, status); 1550 1551 while (TRUE) 1552 { 1553 switch (pWhalBus->uLoadStage) 1554 { 1555 case 0: 1556 pWhalBus->uLoadStage = 1; 1557 /* 1558 * Extract and calculate a length of the firmware image 1559 * Needed to avoid DWORD alignment issues 1560 * Get the data length of the firmware image 1561 */ 1562 pWhalBus->uFwDataLen = (pWhalBus->pFwBuf[4] << 24) | 1563 (pWhalBus->pFwBuf[5] << 16) | 1564 (pWhalBus->pFwBuf[6] << 8 ) | 1565 (pWhalBus->pFwBuf[7]); 1566 1567 /* Check the data length */ 1568 if ((pWhalBus->uFwDataLen % 4) != 0) 1569 { 1570 WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, ("FW image length\n")); 1571 1572 } 1573 1574 #if defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI) 1575 status = TNETWIF_SetPartitionsOpt (pWhalBus->hTNETWIF, 1576 HW_ACCESS_DOWNLOAD, 1577 ADDR_OFFS, 1578 module_id, 1579 (TNETWIF_callback_t)whal_FwCtrl_LoadFwImageSm, 1580 hWhalBus); 1581 EXCEPT_L (pWhalBus, status); 1582 #endif 1583 continue; 1584 1585 case 1: 1586 pWhalBus->uLoadStage = 2; 1587 1588 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 1589 ("Image addr=0x%x, Len=0x%x\n", 1590 pWhalBus->pFwBuf, pWhalBus->uFwLastAddr)); 1591 1592 pWhalBus->uChunkNum = 0; 1593 pWhalBus->uPartitionLimit = HW_ACCESS_DOWN_PART0_SIZE; 1594 1595 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("DOWNLOADING !!!\n")); 1596 continue; 1597 1598 case 2: 1599 1600 /* Retrieve the data that was saved for the last chunk */ 1601 #ifdef USE_NO_CHUNK_COPY 1602 if (pWhalBus->uChunkNum > 0) 1603 os_memoryCopy (pWhalBus->hOs, 1604 (void *)(pWhalBus->pFwBuf + FW_HDR_SIZE + (pWhalBus->uChunkNum - 1) * CHUNK_SIZE - TNETWIF_WRITE_OFFSET_BYTES), 1605 (void *)pWhalBus->auFwTmpBuf, 1606 TNETWIF_WRITE_OFFSET_BYTES); 1607 #endif 1608 1609 /* Load firmware by chunks */ 1610 if (pWhalBus->uChunkNum < pWhalBus->uFwDataLen / CHUNK_SIZE) 1611 { 1612 pWhalBus->uLoadStage = 3; 1613 1614 #if defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI) 1615 /* Change partition */ 1616 if (ADDR_OFFS + (pWhalBus->uChunkNum + 2) * CHUNK_SIZE > pWhalBus->uPartitionLimit) 1617 { 1618 pWhalBus->uPartitionLimit = (ADDR_OFFS + pWhalBus->uChunkNum * CHUNK_SIZE) + HW_ACCESS_DOWN_PART0_SIZE; 1619 status = TNETWIF_SetPartitionsOpt (pWhalBus->hTNETWIF, 1620 HW_ACCESS_DOWNLOAD, 1621 ADDR_OFFS + pWhalBus->uChunkNum * CHUNK_SIZE, 1622 module_id, 1623 (TNETWIF_callback_t)whal_FwCtrl_LoadFwImageSm, 1624 hWhalBus); 1625 EXCEPT_L (pWhalBus, status); 1626 1627 WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, 1628 ("Change partition ADDR_OFFS = 0x%x\n", 1629 ADDR_OFFS + pWhalBus->uChunkNum * CHUNK_SIZE)); 1630 } 1631 #endif 1632 } 1633 else 1634 pWhalBus->uLoadStage = 4; 1635 continue; 1636 1637 case 3: 1638 pWhalBus->uLoadStage = 2; 1639 1640 /* Write the data chunk of 512 bytes */ 1641 1642 #ifdef USE_NO_CHUNK_COPY 1643 /* 1644 * Save the chunk trailer bytes in the temporary buffer. 1645 * The trailer space is used by the WSPI driver 1646 */ 1647 os_memoryCopy (pWhalBus->hOs, 1648 (void *)pWhalBus->auFwTmpBuf, 1649 (void *)(pWhalBus->pFwBuf + FW_HDR_SIZE + pWhalBus->uChunkNum * CHUNK_SIZE - TNETWIF_WRITE_OFFSET_BYTES), 1650 TNETWIF_WRITE_OFFSET_BYTES); 1651 #else 1652 /* Copy image chunk to temporary buffer */ 1653 os_memoryCopy (pWhalBus->hOs, 1654 (void *)&pWhalBus->auFwTmpBuf[TNETWIF_WRITE_OFFSET_BYTES], 1655 (void *)(pWhalBus->pFwBuf + FW_HDR_SIZE + pWhalBus->uChunkNum * CHUNK_SIZE), 1656 CHUNK_SIZE); 1657 #endif 1658 1659 /* Load the chunk. Save TNETWIF_WRITE_OFFSET_BYTES space for WSPI bus command */ 1660 status = TNETWIF_WriteMemOpt (pWhalBus->hTNETWIF, 1661 ADDR_OFFS + pWhalBus->uChunkNum * CHUNK_SIZE, 1662 #ifdef USE_NO_CHUNK_COPY 1663 pWhalBus->pFwBuf + FW_HDR_SIZE + pWhalBus->uChunkNum * CHUNK_SIZE - TNETWIF_WRITE_OFFSET_BYTES, 1664 #else 1665 pWhalBus->auFwTmpBuf, 1666 #endif 1667 CHUNK_SIZE, 1668 module_id, 1669 (TNETWIF_callback_t)whal_FwCtrl_LoadFwImageSm, 1670 hWhalBus); 1671 1672 /* Increment chunk number */ 1673 pWhalBus->uChunkNum ++; 1674 1675 /* Log ERROR if the TNETWIF_WriteMemOpt returned ERROR */ 1676 if (status == TNETWIF_ERROR) 1677 { 1678 WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, 1679 ("TNETWIF_WriteMemOpt retruned status=0x%x\n", status)); 1680 } 1681 1682 EXCEPT_L (pWhalBus, status); 1683 continue; 1684 1685 case 4: 1686 pWhalBus->uLoadStage = 5; 1687 1688 #ifdef USE_NO_CHUNK_COPY 1689 /* 1690 * Save the chunk trailer bytes in the temporary buffer. 1691 * The trailer space is used by the WSPI driver 1692 */ 1693 os_memoryCopy (pWhalBus->hOs, 1694 (void *)pWhalBus->auFwTmpBuf, 1695 (void *)(pWhalBus->pFwBuf + FW_HDR_SIZE + pWhalBus->uChunkNum * CHUNK_SIZE - TNETWIF_WRITE_OFFSET_BYTES), 1696 TNETWIF_WRITE_OFFSET_BYTES); 1697 #else 1698 /* Copy the last image chunk */ 1699 os_memoryCopy (pWhalBus->hOs, 1700 (void *)&pWhalBus->auFwTmpBuf[TNETWIF_WRITE_OFFSET_BYTES], 1701 (void *)(pWhalBus->pFwBuf + FW_HDR_SIZE + pWhalBus->uChunkNum * CHUNK_SIZE), 1702 pWhalBus->uFwDataLen % CHUNK_SIZE); 1703 #endif 1704 1705 /* Load the last chunk */ 1706 status = TNETWIF_WriteMemOpt (pWhalBus->hTNETWIF, 1707 ADDR_OFFS + pWhalBus->uChunkNum * CHUNK_SIZE, 1708 #ifdef USE_NO_CHUNK_COPY 1709 pWhalBus->pFwBuf + FW_HDR_SIZE + pWhalBus->uChunkNum * CHUNK_SIZE - TNETWIF_WRITE_OFFSET_BYTES, 1710 #else 1711 pWhalBus->auFwTmpBuf, 1712 #endif 1713 pWhalBus->uFwDataLen % CHUNK_SIZE, 1714 module_id, 1715 (TNETWIF_callback_t)whal_FwCtrl_LoadFwImageSm, 1716 hWhalBus); 1717 1718 EXCEPT_L (pWhalBus, status); 1719 continue; 1720 1721 case 5: 1722 pWhalBus->uLoadStage = 0; 1723 1724 /* The download has completed */ 1725 WLAN_OS_REPORT (("Finished downloading firmware.\n")); 1726 1727 #ifdef USE_NO_CHUNK_COPY 1728 /* Retrieve the data that was saved for the last chunk */ 1729 os_memoryCopy (pWhalBus->hOs, 1730 (void *)(pWhalBus->pFwBuf + FW_HDR_SIZE + pWhalBus->uChunkNum * CHUNK_SIZE - TNETWIF_WRITE_OFFSET_BYTES), 1731 (void *)pWhalBus->auFwTmpBuf, 1732 TNETWIF_WRITE_OFFSET_BYTES); 1733 #endif 1734 1735 /* Finalize download (run firmware) */ 1736 pWhalBus->uFinStage = 0; 1737 status = whal_FwCtrl_FinalizeDownloadSm (hWhalBus, module_id, OK); 1738 1739 return status; 1740 1741 } /* End switch */ 1742 1743 } /* End while */ 1744 1745 } 1746 1747 1748 UINT32 whalBus_FwCtrl_GetRadioStandByState(TI_HANDLE hWhalBus) 1749 { 1750 #ifdef USE_SYNC_API 1751 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 1752 UINT32 data; 1753 1754 return TNETWIF_ReadRegSync (pWhalBus->hTNETWIF,GPIO_IN,&data); 1755 1756 #else 1757 1758 return 0; 1759 1760 #endif 1761 } 1762 1763 1764 int whalBus_FwCtrl_Reset(TI_HANDLE hWhalBus) 1765 { 1766 #ifdef USE_SYNC_API 1767 1768 return whal_FwCtrl_Reset (hWhalBus); 1769 1770 #else 1771 1772 return OK; 1773 1774 #endif 1775 } 1776 1777 1778 int whalBus_FwCtrl_isCardIn(TI_HANDLE hWhalBus) 1779 { 1780 #ifdef USE_SYNC_API 1781 1782 /* 1783 UINT32 ChipId; 1784 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 1785 TNETWIF_ReadRegSync(pWhalBus->hTNETWIF,CHIP_ID,&ChipId) 1786 ChipId = CHIP_ID_1X50; 1787 */ 1788 1789 #endif 1790 1791 return TRUE; 1792 } 1793 1794 void whalBus_FwCtrl_Halt(TI_HANDLE hWhalBus) 1795 { 1796 #ifdef USE_SYNC_API 1797 whalBus_T *pWhalBus = (whalBus_T *)hWhalBus; 1798 1799 /* Halt the firmware */ 1800 TNETWIF_RegIsBitSet(pWhalBus->hTNETWIF, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT); 1801 #endif 1802 } 1803
