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    Searched refs:SRL (Results 1 - 8 of 8) sorted by null

/external/libffi/src/mips/
ffitarget.h	128 # define SRL srl 135 # define SRL dsrl
n32.S	119 SRL t4, t6, 1*FFI_FLAG_BITS 132 SRL t4, t6, 2*FFI_FLAG_BITS 145 SRL t4, t6, 3*FFI_FLAG_BITS 158 SRL t4, t6, 4*FFI_FLAG_BITS 171 SRL t4, t6, 5*FFI_FLAG_BITS 184 SRL t4, t6, 6*FFI_FLAG_BITS 197 SRL t4, t6, 7*FFI_FLAG_BITS 219 SRL t6, 8*FFI_FLAG_BITS
o32.S	80 SRL t2, t0, 4 # shift our arg info
/external/openssl/crypto/sha/asm/
sha512-sparcv9.pl	59 $SRL="srlx"; # shift right logical 85 $SRL="srl"; # shift right logical 222 $SRL $e,@Sigma1[0],$h !! $i 226 $SRL $e,@Sigma1[1],$tmp0 230 $SRL $e,@Sigma1[2],$tmp0 237 $SRL $a,@Sigma0[0],$h 242 $SRL $a,@Sigma0[1],$tmp0 246 $SRL $a,@Sigma0[2],$tmp0 276 srl $xi,@sigma0[0],$T1 !! Xupdate($i     [all...]
/external/v8/src/mips/
constants-mips.cc	237 case SRL:
constants-mips.h	214 SRL = ((0 << 3) + 2),
assembler-mips.cc	753 void Assembler::srl(Register rd, Register rt, uint16_t sa) { function in class:v8::internal::Assembler 754 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
simulator-mips.cc	930 case SRL:     [all...]

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