| /external/nist-sip/java/gov/nist/javax/sip/address/ |
| AddressImpl.java | 176 .append(SP);
|
| /external/nist-sip/java/gov/nist/javax/sip/header/ims/ |
| SecurityAgree.java | 122 return this.secMechanism + SEMICOLON + SP + parameters.encode();
|
| /system/core/libpixelflinger/codeflinger/ |
| GGLAssembler.h | 134 mGen.STR(mGen.AL, reg, mGen.SP, mGen.immed12_pre(-4, 1));
136 mGen.STM(mGen.AL, mGen.DB, mGen.SP, 1, mRegList);
146 mGen.LDR(mGen.AL, reg, mGen.SP, mGen.immed12_post(4));
148 mGen.LDM(mGen.AL, mGen.IA, mGen.SP, 1, mRegList);
|
| ARMAssemblerInterface.h | 51 SP = R13,
60 LIST(SP), LIST(LR), LIST(PC),
|
| GGLAssembler.cpp | [all...] |
| /external/nist-sip/java/gov/nist/core/ |
| GenericObjectList.java | 58 protected static final String SP = Separators.SP;
|
| GenericObject.java | 54 protected static final String SP = Separators.SP;
|
| /packages/apps/Email/src/org/apache/james/mime4j/util/ |
| CharsetUtil.java | [all...] |
| /external/nist-sip/java/gov/nist/javax/sip/header/ |
| AuthenticationHeader.java | 158 return this.scheme + SP + parameters.encode();
|
| SIPHeaderList.java | 176 buffer.append(headerName).append(Separators.COLON).append(Separators.SP);
|
| /external/libvpx/vp8/encoder/arm/ |
| mcomp_arm.c | 223 #define SP(x) (((x)&3)<<1) // convert motion vector component to offset for svf calc
224 #define DIST(r,c) svf( PRE(r,c), d->pre_stride, SP(c),SP(r), z,b->src_stride,&sse) // returns subpixel variance error function.
341 #undef SP
935 #undef SP
1047 #undef SP
[all...] |
| /external/libvpx/vp8/encoder/ |
| mcomp.c | 188 #define SP(x) (((x)&3)<<1) // convert motion vector component to offset for svf calc
189 #define DIST(r,c) svf( PRE(r,c), d->pre_stride, SP(c),SP(r), z,b->src_stride,&sse) // returns subpixel variance error function.
306 #undef SP
855 #undef SP
[all...] |
| /external/clearsilver/perl/ |
| ClearSilver.xs | 66 PUSHMARK(SP);
|
| /prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/lib/gcc/i686-unknown-linux-gnu/4.2.1/include/xorg/ |
| assyntax.h | 140 #define SP sp
141 #define ESP sp
202 #define SP %sp
[all...] |
| /external/qemu/ |
| ppc-dis.c | 877 #define SP R + 1
880 #define S SP + 1
[all...] |
| /dalvik/vm/mterp/out/ |
| InterpAsm-armv4t.S | 37 r13 (sp) should be managed carefully in case a signal arrives
49 registers are placed on the stack. "sp" points at the first stacked argument
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
238 * Macro for "LDMFD SP!, {...regs...,PC}".
243 ldmfd sp!, {\regs,pc}
301 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
304 sub sp, sp, #4 @ align 64
311 str sp, [r0, #offGlue_bailPtr] @ save SP for eventual retur
[all...] |
| InterpAsm-armv5te-vfp.S | 37 r13 (sp) should be managed carefully in case a signal arrives
49 registers are placed on the stack. "sp" points at the first stacked argument
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
238 * Macro for "LDMFD SP!, {...regs...,PC}".
243 ldmfd sp!, {\regs,pc}
301 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
304 sub sp, sp, #4 @ align 64
311 str sp, [r0, #offGlue_bailPtr] @ save SP for eventual retur
[all...] |
| InterpAsm-armv5te.S | 37 r13 (sp) should be managed carefully in case a signal arrives
49 registers are placed on the stack. "sp" points at the first stacked argument
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
238 * Macro for "LDMFD SP!, {...regs...,PC}".
243 ldmfd sp!, {\regs,pc}
301 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
304 sub sp, sp, #4 @ align 64
311 str sp, [r0, #offGlue_bailPtr] @ save SP for eventual retur
[all...] |
| InterpAsm-armv7-a-neon.S | 37 r13 (sp) should be managed carefully in case a signal arrives
49 registers are placed on the stack. "sp" points at the first stacked argument
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
238 * Macro for "LDMFD SP!, {...regs...,PC}".
243 ldmfd sp!, {\regs,pc}
311 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
314 sub sp, sp, #4 @ align 64
321 str sp, [r0, #offGlue_bailPtr] @ save SP for eventual retur
[all...] |
| InterpAsm-armv7-a.S | 37 r13 (sp) should be managed carefully in case a signal arrives
49 registers are placed on the stack. "sp" points at the first stacked argument
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
238 * Macro for "LDMFD SP!, {...regs...,PC}".
243 ldmfd sp!, {\regs,pc}
311 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
314 sub sp, sp, #4 @ align 64
321 str sp, [r0, #offGlue_bailPtr] @ save SP for eventual retur
[all...] |
| InterpAsm-x86-atom.S | [all...] |
| /prebuilt/sdk/4/ |
| android.jar | |
| /prebuilt/sdk/7/ |
| android.jar | |
| /prebuilt/sdk/8/ |
| android.jar | |
