/external/dbus/test/data/valid-messages/ |
array-of-array-of-uint32.message | 1 # Message with an array of array of uint32 11 TYPE UINT32 16 ## array of uint32 19 UINT32 1 20 UINT32 2 21 UINT32 3 24 ## array of uint32 27 UINT32 4 28 UINT32 5
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opposite-endian.message | 21 TYPE UINT32 22 UINT32 0xfffffff
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/hardware/broadcom/wlan/bcm4329/src/include/ |
aidmp.h | 118 uint32 oobselina30; 119 uint32 oobselina74; 120 uint32 PAD[6]; 121 uint32 oobselinb30; 122 uint32 oobselinb74; 123 uint32 PAD[6]; 124 uint32 oobselinc30; 125 uint32 oobselinc74; 126 uint32 PAD[6]; 127 uint32 oobselind30; [all...] |
wlioctl.h | 48 uint32 packetId; 76 uint32 cnt_rxundec; 77 uint32 cnt_rxframe; 95 uint32 version; 96 uint32 length; 113 uint32 nbss_cap; 115 uint32 reserved32[1]; 121 uint32 ie_length; 127 uint32 SSID_len; 167 uint32 version [all...] |
siutils.h | 41 uint32 cccaps; 43 uint32 pmucaps; 50 uint32 chipst; 113 typedef void (*gpio_handler_t)(uint32 stat, void *arg); 135 extern void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val); 136 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); 137 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val) [all...] |
bcmpcispi.h | 64 uint32 spih_ctrl; /* 0x00 SPI Control Register */ 65 uint32 spih_stat; /* 0x04 SPI Status Register */ 66 uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */ 67 uint32 spih_ext; /* 0x0C SPI Extension Register */ 68 uint32 PAD[4]; /* 0x10-0x1F PADDING */ 70 uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */ 71 uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */ 72 uint32 PAD[6]; /* 0x28-0x3F PADDING */ 74 uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */ 75 uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, * [all...] |
hndrte_armtrap.h | 64 uint32 type; 65 uint32 epc; 66 uint32 cpsr; 67 uint32 spsr; 68 uint32 r0; 69 uint32 r1; 70 uint32 r2; 71 uint32 r3; 72 uint32 r4; 73 uint32 r5 [all...] |
sbhnddma.h | 39 uint32 control; 40 uint32 addr; 41 uint32 ptr; 42 uint32 status; 51 uint32 fifoaddr; 52 uint32 fifodatalow; 53 uint32 fifodatahigh; 54 uint32 pad; 59 uint32 ctrl; 60 uint32 addr; [all...] |
sbsocram.h | 42 uint32 coreinfo; 43 uint32 bwalloc; 44 uint32 extracoreinfo; 45 uint32 biststat; 46 uint32 bankidx; 47 uint32 standbyctrl; 49 uint32 errlogstatus; 50 uint32 errlogaddr; 52 uint32 cambankidx; 53 uint32 cambankstandbyctrl [all...] |
sbconfig.h | 81 uint32 PAD[2]; 82 uint32 sbipsflag; 83 uint32 PAD[3]; 84 uint32 sbtpsflag; 85 uint32 PAD[11]; 86 uint32 sbtmerrloga; 87 uint32 PAD; 88 uint32 sbtmerrlog; 89 uint32 PAD[3]; 90 uint32 sbadmatch3; [all...] |
/external/qemu/gdb-xml/ |
power-core.xml | 10 <reg name="r0" bitsize="32" type="uint32"/> 11 <reg name="r1" bitsize="32" type="uint32"/> 12 <reg name="r2" bitsize="32" type="uint32"/> 13 <reg name="r3" bitsize="32" type="uint32"/> 14 <reg name="r4" bitsize="32" type="uint32"/> 15 <reg name="r5" bitsize="32" type="uint32"/> 16 <reg name="r6" bitsize="32" type="uint32"/> 17 <reg name="r7" bitsize="32" type="uint32"/> 18 <reg name="r8" bitsize="32" type="uint32"/> 19 <reg name="r9" bitsize="32" type="uint32"/> [all...] |
/external/dbus/test/data/invalid-messages/ |
array-with-mixed-types.message | 23 TYPE UINT32 28 ## array of uint32 31 UINT32 1 32 UINT32 2 33 UINT32 3 36 ## array of uint32 39 UINT32 4 40 UINT32 5
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too-short-dict.message | 23 STRING 'uint32' 24 TYPE UINT32 25 UINT32 0x8765432 26 STRING 'uint32'
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/hardware/ril/mock-ril/src/proto/ |
msgheader.proto | 9 required uint32 cmd = 1; 10 required uint32 length_data = 2; 11 optional uint32 status = 3;
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/system/wlan/ti/sta_dk_4_0_4_32/common/src/TNETW_Driver/TNETWIF/Inc/ |
whalHwAccess.h | 122 int whal_hwAccess_Config(TI_HANDLE hHwAccess, TI_HANDLE hReport,UINT32 RegBaseAddr, UINT32 MemBaseAddr, HwAccess_callback_t CBFunc,void* CBArg); 124 int whal_hwAccess_SetPartitions(TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start); 125 int whal_hwAccess_SetPartitionsAsync(TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start); 127 int whal_hwAccess_WriteELP(TI_HANDLE hHwAccess, UINT32 data); 128 int whal_hwAccess_WriteELPAsync(TI_HANDLE hHwAccess, UINT32 data, BOOL bCb, BOOL bMore); 131 int whal_hwAccess_ReadMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 132 int whal_hwAccess_WriteMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 133 int whal_hwAccess_ReadMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 134 int whal_hwAccess_WriteMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len) [all...] |
/frameworks/base/media/libstagefright/codecs/m4v_h263/dec/src/ |
get_pred_outside.cpp | 116 *((uint32*)ptr) = temp; \ 117 *((uint32*)(ptr+4)) = temp; \ 118 *((uint32*)(ptr+=16)) = temp; \ 119 *((uint32*)(ptr+4)) = temp; \ 120 *((uint32*)(ptr+=16)) = temp; \ 121 *((uint32*)(ptr+4)) = temp; \ 122 *((uint32*)(ptr+=16)) = temp; \ 123 *((uint32*)(ptr+4)) = temp; \ 124 *((uint32*)(ptr+=16)) = temp; \ 125 *((uint32*)(ptr+4)) = temp; [all...] |
/system/wlan/ti/sta_dk_4_0_4_32/common/src/core/mlme/ |
mlmeParser.h | 87 UINT32 dataLen, 88 UINT32 *pReadLen, 93 UINT32 dataLen, 94 UINT32 *pReadLen, 100 UINT32 dataLen, 101 UINT32 *pReadLen, 106 UINT32 dataLen, 107 UINT32 *pReadLen, 112 UINT32 dataLen, 113 UINT32 *pReadLen, [all...] |
/external/clearsilver/util/ |
neo_hash.h | 20 typedef UINT32 (*NE_HASH_FUNC)(const void *); 27 UINT32 hashv; 33 UINT32 size; 34 UINT32 num; 50 UINT32 ne_hash_str_hash(const void *a); 53 UINT32 ne_hash_int_hash(const void *a);
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/system/wlan/ti/sta_dk_4_0_4_32/common/src/TNETW_Driver/TNETWIF/Export_Inc/ |
TNETWIF.h | 114 UINT32 uInitStage; 115 UINT32 uRegBaseAddr; 116 UINT32 uMemBaseAddr; 125 TI_STATUS TNETWIF_Config (TI_HANDLE hTNETWIF, TI_HANDLE hReport, UINT32 uRegBaseAddr, UINT32 uMemBaseAddr, TNETWIF_callback_t fCb, TI_HANDLE hCb); 157 TI_STATUS TNETWIF_SetPartitionsOpt (TI_HANDLE hTNETWIF, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start, UINT8 module_id, TNETWIF_callback_t CBFunc, TI_HANDLE CB_Handle); 165 TI_STATUS TNETWIF_ReadMemOpt (TI_HANDLE hTNETWIF, UINT32 addr, UINT8* data, UINT32 len, UINT8 module_id, TNETWIF_callback_t CBFunc, TI_HANDLE CB_Handle); 166 TI_STATUS TNETWIF_WriteMemOpt (TI_HANDLE hTNETWIF, UINT32 addr, UINT8* data, UINT32 len, UINT8 module_id, TNETWIF_callback_t CBFunc, TI_HANDLE CB_Handle) [all...] |
/external/chromium/base/ |
rand_util_win.cc | 14 uint32 RandUint32() { 15 uint32 number; 25 uint32 first_half = RandUint32(); 26 uint32 second_half = RandUint32();
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/external/giflib/ |
config.h | 11 typedef uint32_t UINT32;
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/hardware/broadcom/wlan/bcm4329/src/shared/ |
siutils_priv.h | 37 typedef uint32 (*si_intrsoff_t)(void *intr_arg); 38 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 45 uint32 event; 54 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */ 55 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */ 56 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */ 57 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */ 58 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */ 59 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */ 61 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper * [all...] |
/external/qemu/distrib/sdl-1.2.12/src/video/ataricommon/ |
SDL_ataric2p_s.h | 36 Uint32 width, /* Dimensions of screen to convert */ 37 Uint32 height, 38 Uint32 dblligne, /* Double the lines when converting ? */ 39 Uint32 srcpitch, /* Length of one source line in bytes */ 40 Uint32 dstpitch /* Length of one destination line in bytes */ 50 Uint32 width, /* Dimensions of screen to convert */ 51 Uint32 height, 52 Uint32 dblligne, /* Double the lines when converting ? */ 53 Uint32 srcpitch, /* Length of one source line in bytes */ 54 Uint32 dstpitch /* Length of one destination line in bytes * [all...] |
/system/wlan/ti/sta_dk_4_0_4_32/common/src/core/data_ctrl/Tx/ |
tx.h | 70 UINT32 dbgDropedPacketsCounter; /* Pkts that failed to be inserted into Q */ 71 UINT32 dbgInsertToMsduListBytes[MAX_NUM_OF_TX_QUEUES]; /* Bytes inserted into Q */ 72 UINT32 dbgInsertToMsduListPackets[MAX_NUM_OF_TX_QUEUES]; /* Pkts that inserted into Q */ 73 UINT32 dbgDropedFromMsduListPackets[MAX_NUM_OF_TX_QUEUES]; /* Pkts that failed to be inserted into Q */ 74 UINT32 dbgScheduledOutPackets[MAX_NUM_OF_TX_QUEUES]; /* Pkts scheduled for transmission per Q */ 75 UINT32 dbgSendToGwsiQosPackets[MAX_NUM_OF_TX_QUEUES]; /* Pkts sent to GWSI layer */ 76 UINT32 dbgDroppedDueExpiryTimePackets[MAX_NUM_OF_TX_QUEUES]; /* Pkts dropped due to expiry time */ 77 UINT32 dbgNumOfMsduFreeInTxTransfer[MAX_NUM_OF_TX_QUEUES]; /* Pkts freed on XFER */ 78 UINT32 dbgNumOfMsduTxTransferCB[MAX_NUM_OF_TX_QUEUES]; /* num of XFER done CB calls */ 79 UINT32 dbgNumOfMsduXferDoneInShceduler[MAX_NUM_OF_TX_QUEUES]; /* Pkts for which XFER done was received in (…) [all...] |
/packages/inputmethods/PinyinIME/jni/include/ |
userdict.h | 85 void set_limit(uint32 max_lemma_count, uint32 max_lemma_size, 86 uint32 reclaim_ratio); 124 uint32 version; 128 uint32 disk_size; 129 uint32 lemma_count; 130 uint32 lemma_size; 131 uint32 delete_count; 132 uint32 delete_size; 134 uint32 sync_count [all...] |