Lines Matching refs:cmd
41 volatile unsigned cmd;
49 ch->cmd = DMOV_CMD_PTR(id);
73 writel(DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(paddr(ptr)), ch.cmd);
99 dmov_s *cmd = cmdlist;
109 cmd[0].cmd = 0 | CMD_OCB;
110 cmd[0].src = paddr(&data[0]);
111 cmd[0].dst = NAND_FLASH_CHIP_SELECT;
112 cmd[0].len = 4;
114 cmd[1].cmd = DST_CRCI_NAND_CMD;
115 cmd[1].src = paddr(&data[1]);
116 cmd[1].dst = NAND_FLASH_CMD;
117 cmd[1].len = 4;
119 cmd[2].cmd = 0;
120 cmd[2].src = paddr(&data[2]);
121 cmd[2].dst = NAND_EXEC_CMD;
122 cmd[2].len = 4;
124 cmd[3].cmd = SRC_CRCI_NAND_DATA;
125 cmd[3].src = NAND_FLASH_STATUS;
126 cmd[3].dst = paddr(&data[3]);
127 cmd[3].len = 4;
129 cmd[4].cmd = CMD_OCU | CMD_LC;
130 cmd[4].src = NAND_READ_ID;
131 cmd[4].dst = paddr(&data[4]);
132 cmd[4].len = 4;
134 ptr[0] = (paddr(cmd) >> 3) | CMD_PTR_LP;
150 dmov_s *cmd = cmdlist;
166 cmd[0].cmd = DST_CRCI_NAND_CMD | CMD_OCB;
167 cmd[0].src = paddr(&data[0]);
168 cmd[0].dst = NAND_FLASH_CMD;
169 cmd[0].len = 16;
171 cmd[1].cmd = 0;
172 cmd[1].src = paddr(&data[6]);
173 cmd[1].dst = NAND_DEV0_CFG0;
174 cmd[1].len = 8;
176 cmd[2].cmd = 0;
177 cmd[2].src = paddr(&data[4]);
178 cmd[2].dst = NAND_EXEC_CMD;
179 cmd[2].len = 4;
181 cmd[3].cmd = SRC_CRCI_NAND_DATA | CMD_OCU | CMD_LC;
182 cmd[3].src = NAND_FLASH_STATUS;
183 cmd[3].dst = paddr(&data[5]);
184 cmd[3].len = 4;
186 ptr[0] = (paddr(cmd) >> 3) | CMD_PTR_LP;
204 unsigned cmd;
221 dmov_s *cmd = cmdlist;
228 data->cmd = NAND_CMD_PAGE_READ_ECC;
242 cmd->cmd = CMD_OCB;
243 cmd->src = NAND_EBI2_ECC_BUF_CFG;
244 cmd->dst = paddr(&data->ecc_cfg_save);
245 cmd->len = 4;
246 cmd++;
249 /* write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst */
250 cmd->cmd = DST_CRCI_NAND_CMD;
251 cmd->src = paddr(&data->cmd);
252 cmd->dst = NAND_FLASH_CMD;
253 cmd->len = ((n == 0) ? 16 : 4);
254 cmd++;
257 /* block on cmd ready, set configuration */
258 cmd->cmd = 0;
259 cmd->src = paddr(&data->cfg0);
260 cmd->dst = NAND_DEV0_CFG0;
261 cmd->len = 8;
262 cmd++;
265 cmd->cmd = 0;
266 cmd->src = paddr(&data->ecc_cfg);
267 cmd->dst = NAND_EBI2_ECC_BUF_CFG;
268 cmd->len = 4;
269 cmd++;
272 cmd->cmd = 0;
273 cmd->src = paddr(&data->exec);
274 cmd->dst = NAND_EXEC_CMD;
275 cmd->len = 4;
276 cmd++;
279 cmd->cmd = SRC_CRCI_NAND_DATA;
280 cmd->src = NAND_FLASH_STATUS;
281 cmd->dst = paddr(&data->result[n]);
282 cmd->len = 8;
283 cmd++;
286 cmd->cmd = 0;
287 cmd->src = NAND_FLASH_BUFFER;
288 cmd->dst = addr + n * 516;
289 cmd->len = ((n < 3) ? 516 : 500);
290 cmd++;
294 cmd->cmd = 0;
295 cmd->src = NAND_FLASH_BUFFER + 500;
296 cmd->dst = spareaddr;
297 cmd->len = 16;
298 cmd++;
301 cmd->cmd = CMD_OCU | CMD_LC;
302 cmd->src = paddr(&data->ecc_cfg_save);
303 cmd->dst = NAND_EBI2_ECC_BUF_CFG;
304 cmd->len = 4;
336 dmov_s *cmd = cmdlist;
343 data->cmd = NAND_CMD_PRG_PAGE;
357 cmd->cmd = CMD_OCB;
358 cmd->src = NAND_EBI2_ECC_BUF_CFG;
359 cmd->dst = paddr(&data->ecc_cfg_save);
360 cmd->len = 4;
361 cmd++;
364 /* write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst */
365 cmd->cmd = DST_CRCI_NAND_CMD;
366 cmd->src = paddr(&data->cmd);
367 cmd->dst = NAND_FLASH_CMD;
368 cmd->len = ((n == 0) ? 16 : 4);
369 cmd++;
373 cmd->cmd = 0;
374 cmd->src = paddr(&data->cfg0);
375 cmd->dst = NAND_DEV0_CFG0;
376 cmd->len = 8;
377 cmd++;
380 cmd->cmd = 0;
381 cmd->src = paddr(&data->ecc_cfg);
382 cmd->dst = NAND_EBI2_ECC_BUF_CFG;
383 cmd->len = 4;
384 cmd++;
388 cmd->cmd = 0;
389 cmd->src = addr + n * 516;
390 cmd->dst = NAND_FLASH_BUFFER;
391 cmd->len = ((n < 3) ? 516 : 510);
392 cmd++;
396 cmd->cmd = 0;
397 cmd->src = spareaddr;
398 cmd->dst = NAND_FLASH_BUFFER + 500;
399 cmd->len = 16;
400 cmd++;
404 cmd->cmd = 0;
405 cmd->src = paddr(&data->exec);
406 cmd->dst = NAND_EXEC_CMD;
407 cmd->len = 4;
408 cmd++;
411 cmd->cmd = SRC_CRCI_NAND_DATA;
412 cmd->src = NAND_FLASH_STATUS;
413 cmd->dst = paddr(&data->result[n]);
414 cmd->len = 8;
415 cmd++;
419 cmd->cmd = CMD_OCU | CMD_LC;
420 cmd->src = paddr(&data->ecc_cfg_save);
421 cmd->dst = NAND_EBI2_ECC_BUF_CFG;
422 cmd->len = 4;
450 cmdlist[0].cmd = CMD_OCB;
455 cmdlist[1].cmd = CMD_OCU | CMD_LC;
475 | (1 << 31) /* Send read cmd */
