Lines Matching refs:x00
36 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
59 #define UART_FCR_R_TRIG_00 0x00
63 #define UART_FCR_T_TRIG_00 0x00
69 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
74 #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
78 #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
95 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
185 #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
191 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
196 #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
216 #define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
233 #define UART_ACR 0x00 /* Additional Control Register */
