Lines Matching refs:PhysReg
190 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
191 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
192 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
193 PhysReg2LiveUnion[PhysReg].verify(VRegs);
206 unsigned PhysReg = VRM->getPhys(reg);
207 if (!unionVRegs[PhysReg].test(reg)) {
209 TRI->getName(PhysReg) << "\n";
277 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
279 << " to " << PrintReg(PhysReg, TRI) << '\n');
281 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
282 MRI->setPhysRegUsed(PhysReg);
283 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
287 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
289 << " from " << PrintReg(PhysReg, TRI) << '\n');
290 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
291 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
369 unsigned PhysReg) {
370 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
378 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
380 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
388 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
392 unassign(SpilledVReg, PhysReg);
403 // Spill or split all live virtual registers currently unified under PhysReg
407 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
413 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
420 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
424 // Spill each interfering vreg allocated to PhysReg or an alias.
425 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
438 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
439 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
450 if (!MBB->isLiveIn(PhysReg))
451 MBB->addLiveIn(PhysReg);
489 unsigned PhysReg = *I;
493 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
496 return PhysReg;
504 PhysRegSpillCands.push_back(PhysReg);
