Lines Matching refs:MO
191 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
194 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
195 // Check for non-debug uses or defs following MO.
197 MachineOperand *Next = &MO;
204 if (StackSlotForVirtReg[MO.getReg()] != -1)
207 // Check that the use/def chain has exactly one operand - MO.
208 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
214 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
215 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
216 if (MO.getReg() == LR.PhysReg)
217 MO.setIsKill();
323 /// This may add implicit kills to MO->getParent() and invalidate MO.
324 void RAFast::usePhysReg(MachineOperand &MO) {
325 unsigned PhysReg = MO.getReg();
337 MO.setIsKill();
357 MO.getParent()->addRegisterKilled(Alias, TRI, true);
363 MO.getParent()->addRegisterKilled(Alias, TRI, true);
377 MO.setIsKill();
583 MachineOperand &MO = MI->getOperand(OpNum);
593 if (isLastUseOfLocalReg(MO)) {
594 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
595 if (MO.isUse())
596 MO.setIsKill();
598 MO.setIsDead();
599 } else if (MO.isKill()) {
600 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
601 MO.setIsKill(false);
602 } else if (MO.isDead()) {
603 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
604 MO.setIsDead(false);
606 } else if (MO.isKill()) {
611 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
612 MO.setIsKill(false);
613 } else if (MO.isDead()) {
614 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
615 MO.setIsDead(false);
628 MachineOperand &MO = MI->getOperand(OpNum);
629 if (!MO.getSubReg()) {
630 MO.setReg(PhysReg);
631 return MO.isKill() || MO.isDead();
635 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
636 MO.setSubReg(0);
640 if (MO.isKill()) {
644 return MO.isDead();
654 MachineOperand &MO = MI->getOperand(i);
655 if (!MO.isReg()) continue;
656 unsigned Reg = MO.getReg();
659 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
660 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
670 MachineOperand &MO = MI->getOperand(i);
671 if (!MO.isReg() || !MO.isDef()) continue;
672 unsigned Reg = MO.getReg();
687 MachineOperand &MO = MI->getOperand(i);
688 if (!MO.isReg()) continue;
689 unsigned Reg = MO.getReg();
691 if (MO.isUse()) {
694 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
701 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
702 DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
707 } else if (MO.isEarlyClobber()) {
708 // Note: defineVirtReg may invalidate MO.
719 MachineOperand &MO = MI->getOperand(i);
720 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
721 unsigned Reg = MO.getReg();
814 MachineOperand &MO = MI->getOperand(i);
815 if (!MO.isReg()) continue;
816 unsigned Reg = MO.getReg();
827 MO.setReg(0);
848 MO.setReg(0);
879 MachineOperand &MO = MI->getOperand(i);
880 if (!MO.isReg()) continue;
881 unsigned Reg = MO.getReg();
885 if (MO.isUse()) {
889 if (MO.isEarlyClobber())
891 if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
897 if (MO.isUse()) {
898 usePhysReg(MO);
899 } else if (MO.isEarlyClobber()) {
900 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
929 MachineOperand &MO = MI->getOperand(i);
930 if (!MO.isReg()) continue;
931 unsigned Reg = MO.getReg();
933 if (MO.isUse()) {
949 MachineOperand &MO = MI->getOperand(i);
950 if (!MO.isReg()) continue;
951 unsigned Reg = MO.getReg();
954 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
979 MachineOperand &MO = MI->getOperand(i);
980 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
982 unsigned Reg = MO.getReg();
986 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
