Lines Matching full:srl
838 else if (Opc == ISD::SRL)
1071 case ISD::SRL: return visitSRL(N);
1147 case ISD::SRL:
1796 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1799 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1800 AddToWorkList(SRL.getNode());
1851 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1865 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
2009 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2045 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2128 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2158 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2242 // For each of OP in SHL/SRL/SRA/AND...
2246 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2370 // fold (and (sra)) -> (and (srl)) when possible.
2507 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2510 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2534 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2536 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2549 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2575 // Make sure everything beyond the low halfword is zero since the SRL 16
2585 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2598 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2621 if (N0.getOpcode() != ISD::SRL)
2643 } else { // Opc == ISD::SRL
2729 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2873 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2884 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2905 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2922 // Canonicalize shl to left side in a shl/srl pair.
2934 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2935 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2973 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2974 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2990 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2991 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3020 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3022 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3034 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3036 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3213 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3328 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3329 // (and (srl x, (sub c1, c2), MASK)
3330 if (N1C && N0.getOpcode() == ISD::SRL &&
3344 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3445 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3478 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3503 // If the sign bit is known to be zero, switch this to a SRL.
3505 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3524 // fold (srl c1, c2) -> c1 >>u c2
3526 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3527 // fold (srl 0, x) -> 0
3530 // fold (srl x, c >= size(x)) -> undef
3533 // fold (srl x, 0) -> x
3536 // if (srl x, c) is known to be zero, return 0
3541 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3542 if (N1C && N0.getOpcode() == ISD::SRL &&
3548 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3552 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3554 N0.getOperand(0).getOpcode() == ISD::SRL &&
3567 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3573 // fold (srl (shl x, c), c) -> (and x, cst2)
3582 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3589 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3591 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3599 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3603 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3606 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3614 // zeros, thus the result of the srl will always be zero.
3625 // could be set on input to the CTLZ node. If this bit is set, the SRL
3626 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3627 // to an SRL/XOR pair, which is likely to simplify more.
3632 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3642 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3652 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3662 // fold operands of srl based on knowledge that the low bits are not
3673 // Attempt to convert a srl of a load into a narrower zero-extending load.
3682 // %c = srl i32 %b, 1
3692 // However when after the source operand of SRL is optimized into AND, the SRL
3970 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4183 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4202 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4385 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4431 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4582 case ISD::SRL:
4595 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4624 } else if (Opc == ISD::SRL) {
4625 // Another special-case: SRL is basically zero-extending a narrower value.
4644 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4781 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4786 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4787 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4788 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4789 if (N0.getOpcode() == ISD::SRL) {
4792 // We can turn this into an SRA iff the input to the SRL is already sign
4891 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5061 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5715 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5718 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5730 // %c = srl i32 %b, 1
5741 // SRL constant is equal to the log2 of the AND constant. The back-end is
5771 // Replace the uses of SRL with SETCC
6362 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
7489 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7496 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7607 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7612 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7616 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7621 return DAG.getNode(ISD::SRL, DL, XType,
7626 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7628 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
