Lines Matching refs:SU
189 /// IsReachable - Checks if SU is reachable from TargetSU.
190 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
191 return Topo.IsReachable(SU, TargetSU);
194 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
196 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
197 return Topo.WillCreateCycle(SU, TargetSU);
200 /// AddPred - adds a predecessor edge to SUnit SU.
203 void AddPred(SUnit *SU, const SDep &D) {
204 Topo.AddPred(SU, D.getSUnit());
205 SU->addPred(D);
208 /// RemovePred - removes a predecessor edge from SUnit SU.
211 void RemovePred(SUnit *SU, const SDep &D) {
212 Topo.RemovePred(SU, D.getSUnit());
213 SU->removePred(D);
217 bool isReady(SUnit *SU) {
219 AvailableQueue->isReady(SU);
222 void ReleasePred(SUnit *SU, const SDep *PredEdge);
223 void ReleasePredecessors(SUnit *SU);
224 void ReleaseSucc(SUnit *SU, const SDep *SuccEdge);
225 void ReleaseSuccessors(SUnit *SU);
228 void AdvancePastStalls(SUnit *SU);
229 void EmitNode(SUnit *SU);
338 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
339 SUnits[su].dumpAll(this));
366 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
382 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
407 /// Always update LiveRegDefs for a register dependence even if the current SU
423 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
425 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
427 ReleasePred(SU, &*I);
434 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
439 LiveRegGens[I->getReg()] = SU;
503 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
512 // if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return;
514 unsigned ReadyCycle = isBottomUp ? SU->getHeight() : SU->getDepth();
525 if (isBottomUp && SU->isCall)
533 HazardRec->getHazardType(SU, isBottomUp ? -Stalls : Stalls);
545 void ScheduleDAGRRList::EmitNode(SUnit *SU) {
550 if (!SU->getNode())
553 switch (SU->getNode()->getOpcode()) {
555 assert(SU->getNode()->isMachineOpcode() &&
571 if (isBottomUp && SU->isCall) {
577 HazardRec->EmitInstruction(SU);
579 if (!isBottomUp && SU->isCall) {
584 static void resetVRegCycle(SUnit *SU);
589 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
591 DEBUG(SU->dump(this));
594 if (CurCycle < SU->getHeight())
595 DEBUG(dbgs() << " Height [" << SU->getHeight()
603 SU->setHeightToAtLeast(CurCycle);
606 EmitNode(SU);
608 Sequence.push_back(SU);
610 AvailableQueue->ScheduledNode(SU);
620 ReleasePredecessors(SU);
623 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
625 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
626 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
634 resetVRegCycle(SU);
636 SU->isScheduled = true;
647 if (SU->getNode() && SU->getNode()->isMachineOpcode())
655 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
672 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
673 DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ");
674 DEBUG(SU->dump(this));
676 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
679 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){
689 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
694 LiveRegDefs[I->getReg()] = SU;
703 if (SU->getHeight() < MinAvailableCycle)
704 MinAvailableCycle = SU->getHeight();
706 SU->setHeightDirty();
707 SU->isScheduled = false;
708 SU->isAvailable = true;
711 SU->isPending = true;
712 PendingQueue.push_back(SU);
715 AvailableQueue->push(SU);
717 AvailableQueue->UnscheduledNode(SU);
733 SUnit *SU = *I;
734 for (; SU->getHeight() > HazardCycle; ++HazardCycle) {
737 EmitNode(SU);
743 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
747 if (SU->isSucc(OldSU))
748 // Don't try to remove SU from AvailableQueue.
749 SU->isAvailable = false;
759 assert(!SU->isSucc(OldSU) && "Something is wrong!");
768 static bool isOperandOf(const SUnit *SU, SDNode *N) {
769 for (const SDNode *SUNode = SU->getNode(); SUNode;
779 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
780 SDNode *N = SU->getNode();
784 if (SU->getNode()->getGluedNode())
808 DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
814 unsigned OldNumVals = SU->getNode()->getNumValues();
816 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
817 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
853 // Record all the edges to and from the old SU, by category.
859 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
868 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
879 RemovePred(SU, Pred);
885 RemovePred(SU, Pred);
891 RemovePred(SU, Pred);
897 D.setSUnit(SU);
909 D.setSUnit(SU);
931 SU = NewSU;
934 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n");
935 NewSU = CreateClone(SU);
938 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
946 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
955 D.setSUnit(SU);
962 AvailableQueue->updateNode(SU);
971 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
986 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1010 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg));
1013 AvailableQueue->updateNode(SU);
1040 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1051 if (LiveRegDefs[*AliasI] == SU) continue;
1065 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
1072 // If SU is the currently live definition of the same register that it uses,
1074 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1076 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1081 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
1101 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1115 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1136 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
1230 DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum
1231 << " to SU #" << Copies.front()->NodeNum << "\n");
1239 DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum
1240 << " to SU #" << TrySU->NodeNum << "\n");
1286 SUnit *SU = PickNodeToScheduleBottomUp();
1288 AdvancePastStalls(SU);
1290 ScheduleNodeBottomUp(SU);
1293 // Advance the cycle to free resources. Skip ahead to the next ready SU.
1313 void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
1334 void ScheduleDAGRRList::ReleaseSuccessors(SUnit *SU) {
1336 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1341 ReleaseSucc(SU, &*I);
1348 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU) {
1350 DEBUG(SU->dump(this));
1352 assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
1353 SU->setDepthToAtLeast(CurCycle);
1354 Sequence.push_back(SU);
1356 ReleaseSuccessors(SU);
1357 SU->isScheduled = true;
1358 AvailableQueue->ScheduledNode(SU);
1407 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
1484 bool isReady(SUnit *SU, unsigned CurCycle) const;
1503 bool isReady(SUnit *SU, unsigned CurCycle) const;
1566 void addNode(const SUnit *SU);
1568 void updateNode(const SUnit *SU);
1576 unsigned getNodePriority(const SUnit *SU) const;
1578 unsigned getNodeOrdering(const SUnit *SU) const {
1579 if (!SU->getNode()) return 0;
1581 return scheduleDAG->DAG->GetOrdering(SU->getNode());
1592 void remove(SUnit *SU) {
1594 assert(SU->NodeQueueId != 0 && "Not in queue!");
1596 SU);
1600 SU->NodeQueueId = 0;
1607 bool HighRegPressure(const SUnit *SU) const;
1609 bool MayReduceRegPressure(SUnit *SU) const;
1611 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1613 void ScheduledNode(SUnit *SU);
1615 void UnscheduledNode(SUnit *SU);
1618 bool canClobber(const SUnit *SU, const SUnit *Op);
1682 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
1684 dbgs() << "Height " << SU->getHeight() << ": ";
1686 dbgs() << "Depth " << SU->getDepth() << ": ";
1687 SU->dump(DAG);
1729 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
1730 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
1735 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1764 void RegReductionPQBase::addNode(const SUnit *SU) {
1768 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1771 void RegReductionPQBase::updateNode(const SUnit *SU) {
1772 SethiUllmanNumbers[SU->NodeNum] = 0;
1773 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1778 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
1779 assert(SU->NodeNum < SethiUllmanNumbers.size());
1780 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1791 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1792 // If SU does not have a register use, i.e. it doesn't produce a value
1798 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1799 // If SU does not have a register def, schedule it close to its uses
1803 return SethiUllmanNumbers[SU->NodeNum];
1805 unsigned Priority = SethiUllmanNumbers[SU->NodeNum];
1806 if (SU->isCallOp) {
1808 int NP = (int)Priority - SU->getNode()->getNumValues();
1831 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1835 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1857 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
1858 const SDNode *N = SU->getNode();
1860 if (!N->isMachineOpcode() || !SU->NumSuccs)
1882 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
1885 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1905 const SDNode *N = SU->getNode();
1907 if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
1922 void RegReductionPQBase::ScheduledNode(SUnit *SU) {
1926 if (!SU->getNode())
1929 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1950 // here with the reduction further below. Note that this SU may use multiple
1970 //assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses");
1971 int SkipRegDefs = (int)SU->NumRegDefsLeft;
1972 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG);
1981 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n");
1991 void RegReductionPQBase::UnscheduledNode(SUnit *SU) {
1995 const SDNode *N = SU->getNode();
2011 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2056 if (SU->NumSuccs && N->isMachineOpcode()) {
2078 static unsigned closestSucc(const SUnit *SU) {
2080 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2097 static unsigned calcMaxScratches(const SUnit *SU) {
2099 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2107 /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
2109 static bool hasOnlyLiveInOpers(const SUnit *SU) {
2111 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2129 /// hasOnlyLiveOutUses - Return true if SU has only value successors that are
2130 /// CopyToReg to a virtual register. This SU def is probably a liveout and
2132 static bool hasOnlyLiveOutUses(const SUnit *SU) {
2134 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2161 static void initVRegCycle(SUnit *SU) {
2165 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
2168 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
2170 SU->isVRegCycle = true;
2172 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2181 static void resetVRegCycle(SUnit *SU) {
2182 if (!SU->isVRegCycle)
2185 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2199 static bool hasVRegCycleUse(const SUnit *SU) {
2200 // If this SU also defines the VReg, don't hoist it as a "use".
2201 if (SU->isVRegCycle)
2204 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2209 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n");
2218 // Note: The ScheduleHazardRecognizer interface requires a non-const SU.
2219 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
2221 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2278 DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
2279 << ") depth " << LDepth << " vs SU (" << right->NodeNum
2305 DEBUG(dbgs() << " SU (" << left->NodeNum << ") "
2306 << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "
2434 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2437 if (SPQ->MayReduceRegPressure(SU)) return true;
2439 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false;
2441 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay)
2463 DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
2469 DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
2483 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2484 if (SU->getHeight() > CurCycle) return false;
2486 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2493 static bool canEnableCoalescing(SUnit *SU) {
2494 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2507 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
2508 // If SU does not have a register def, schedule it close to its uses
2533 DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff
2534 << " != SU(" << right->NodeNum << "): " << RPDiff << "\n");
2547 DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
2548 << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
2565 DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
2566 << left->getDepth() << " != SU(" << right->NodeNum << "): "
2606 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2607 if (SU->isTwoAddress) {
2608 unsigned Opc = SU->getNode()->getMachineOpcode();
2614 SDNode *DU = SU->getNode()->getOperand(i).getNode();
2624 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
2626 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
2633 for (const SDNode *SUNode = SU->getNode(); SUNode;
2692 SUnit *SU = &(*SUnits)[i];
2696 if (SU->NumSuccs != 0)
2699 if (SU->NumPreds != 1)
2703 if (SDNode *N = SU->getNode())
2711 for (SUnit::const_pred_iterator II = SU->Preds.begin(),
2712 EE = SU->Preds.end(); II != EE; ++II)
2723 // Short-circuit the case where SU is PredSU's only data successor.
2728 if (SDNode *N = SU->getNode())
2738 if (PredSuccSU == SU) continue;
2744 if (SU->hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
2745 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI))
2748 if (scheduleDAG->IsReachable(SU, PredSuccSU))
2754 DEBUG(dbgs() << " Prescheduling SU #" << SU->NodeNum
2761 if (SuccSU != SU) {
2764 scheduleDAG->AddPred(SU, Edge);
2765 Edge.setSUnit(SU);
2783 SUnit *SU = &(*SUnits)[i];
2784 if (!SU->isTwoAddress)
2787 SDNode *Node = SU->getNode();
2788 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getGluedNode())
2791 bool isLiveOut = hasOnlyLiveOutUses(SU);
2799 SDNode *DU = SU->getNode()->getOperand(j).getNode();
2808 if (SuccSU == SU)
2812 if (SuccSU->getHeight() < SU->getHeight() &&
2813 (SU->getHeight() - SuccSU->getHeight()) > 1)
2829 if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) {
2830 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
2842 (!SU->isCommutable && SuccSU->isCommutable)) &&
2843 !scheduleDAG->IsReachable(SuccSU, SU)) {
2844 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"
2845 << SU->NodeNum << " to SU #" << SuccSU->NodeNum << "\n");
2846 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0,
2857 /// predecessors of the successors of the SUnit SU. Stop when the provided
2859 static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
2862 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
