Lines Matching refs:PredReg
858 unsigned PredReg, unsigned MIFlags) const {
868 .addImm(0).addImm(Pred).addReg(PredReg)
892 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
895 Pred, PredReg, TII);
898 Pred, PredReg, TII);
931 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
932 unsigned PredReg = Old->getOperand(2).getReg();
933 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
935 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
936 unsigned PredReg = Old->getOperand(3).getReg();
938 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1257 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1265 Offset, Pred, PredReg, TII);
1269 Offset, Pred, PredReg, TII);
