Lines Matching refs:Br
210 bool FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br);
211 bool FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br);
212 bool FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br);
1406 bool ARMConstantIslands::FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br) {
1407 MachineInstr *MI = Br.MI;
1411 if (BBIsInRange(MI, DestBB, Br.MaxDisp))
1414 if (!Br.isCond)
1415 return FixUpUnconditionalBr(MF, Br);
1416 return FixUpConditionalBr(MF, Br);
1424 ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br) {
1425 MachineInstr *MI = Br.MI;
1431 Br.MaxDisp = (1 << 21) * 2;
1449 ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
1450 MachineInstr *MI = Br.MI;
1474 BMI->getOpcode() == Br.UncondBr) {
1483 if (BBIsInRange(MI, NewDest, Br.MaxDisp)) {
1515 Br.MI = &MBB->back();
1517 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1519 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1520 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1607 ImmBranch &Br = ImmBranches[i];
1608 unsigned Opcode = Br.MI->getOpcode();
1628 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1629 if (BBIsInRange(Br.MI, DestBB, MaxOffs)) {
1630 Br.MI->setDesc(TII->get(NewOpc));
1631 MachineBasicBlock *MBB = Br.MI->getParent();
1639 Opcode = Br.MI->getOpcode();
1645 ARMCC::CondCodes Pred = llvm::getInstrPredicate(Br.MI, PredReg);
1652 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1655 unsigned BrOffset = GetOffsetOf(Br.MI) + 4 - 2;
1658 MachineBasicBlock::iterator CmpMI = Br.MI;
1659 if (CmpMI != Br.MI->getParent()->begin()) {
1667 MachineBasicBlock *MBB = Br.MI->getParent();
1669 BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1670 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
1672 Br.MI->eraseFromParent();
1673 Br.MI = NewBR;
