Lines Matching refs:MIB
208 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
210 const MachineInstrBuilder &MIB,
257 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
258 MachineInstr *MI = &*MIB;
264 AddDefaultPred(MIB);
271 AddDefaultT1CC(MIB);
273 AddDefaultCC(MIB);
275 return MIB;
598 MachineInstrBuilder MIB;
602 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
605 MIB.addImm(Id);
608 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
613 AddOptionalDefs(MIB);
618 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRi12),
623 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
628 AddOptionalDefs(MIB);
870 const MachineInstrBuilder &MIB,
889 MIB.addFrameIndex(FI);
892 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
894 MIB.addImm(Addr.Offset);
895 MIB.addMemOperand(MMO);
898 MIB.addReg(Addr.Base.Reg);
901 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
903 MIB.addImm(Addr.Offset);
905 AddOptionalDefs(MIB);
942 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
944 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
1000 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1003 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
1827 MachineInstrBuilder MIB;
1831 MIB
1836 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1842 MIB.addReg(RegArgs[i]);
1849 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1939 MachineInstrBuilder MIB;
1944 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1949 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1955 MIB.addReg(RegArgs[i]);
1962 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2031 MachineInstrBuilder MIB;
2032 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
2035 MIB.addImm(1);
2036 AddOptionalDefs(MIB);
