Lines Matching refs:PredReg
91 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
103 unsigned PredReg,
109 ARMCC::CondCodes Pred, unsigned PredReg,
292 unsigned PredReg, unsigned Scratch, DebugLoc dl,
345 .addImm(Pred).addReg(PredReg).addReg(0);
356 .addImm(Pred).addReg(PredReg);
372 ARMCC::CondCodes Pred, unsigned PredReg,
407 Pred, PredReg, Scratch, dl, Regs))
439 ARMCC::CondCodes Pred, unsigned PredReg,
492 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
493 MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
504 Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
510 ARMCC::CondCodes Pred, unsigned PredReg){
528 MyPredReg == PredReg);
533 ARMCC::CondCodes Pred, unsigned PredReg){
551 MyPredReg == PredReg);
687 unsigned PredReg = 0;
688 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
708 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
712 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
727 isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
730 isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
749 .addImm(Pred).addReg(PredReg);
842 unsigned PredReg = 0;
843 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
856 if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {
860 isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) {
876 isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) {
879 } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) {
910 .addImm(Pred).addReg(PredReg)
918 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
923 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
930 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
935 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1040 ARMCC::CondCodes Pred, unsigned PredReg,
1047 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1053 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1086 unsigned PredReg = 0;
1087 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
1098 .addImm(Pred).addReg(PredReg)
1105 .addImm(Pred).addReg(PredReg)
1128 Pred, PredReg, TII, isT2);
1133 Pred, PredReg, TII, isT2);
1145 Pred, PredReg, TII, isT2);
1150 Pred, PredReg, TII, isT2);
1197 unsigned PredReg = 0;
1198 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MBBI, PredReg);
1216 CurrPredReg = PredReg;
1227 // No need to match PredReg.
1416 unsigned &PredReg, ARMCC::CondCodes &Pred,
1495 int &Offset, unsigned &PredReg,
1557 Pred = llvm::getInstrPredicate(Op0, PredReg);
1655 unsigned BaseReg = 0, PredReg = 0;
1663 Offset, PredReg, Pred, isT2)) {
1683 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1695 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1749 unsigned PredReg = 0;
1750 if (llvm::getInstrPredicate(MI, PredReg) != ARMCC::AL)
