Lines Matching full:registerclass
205 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
222 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
231 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
234 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
240 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
248 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)>;
252 def SPR_8 : RegisterClass<"ARM", [f32], 32, (trunc SPR, 16)>;
258 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
267 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
274 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
280 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
289 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
296 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
304 def QQPR : RegisterClass<"ARM", [v4i64], 256, (sequence "QQ%u", 0, 7)> {
313 def QQPR_VFP2 : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 4)> {
322 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> {
332 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
