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Lines Matching refs:PredReg

55   unsigned PredReg = 0;
56   ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
103   unsigned PredReg = 0;
104   return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
175                                ARMCC::CondCodes Pred, unsigned PredReg,
190         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
197         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
206           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
212           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
399     unsigned PredReg;
400     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
571   unsigned PredReg = 0;
572   ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
573   if (CC == ARMCC::AL || PredReg != ARM::CPSR)
588     ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
605 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
609   return llvm::getInstrPredicate(MI, PredReg);