Lines Matching refs:SPU
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
15 #include "SPU.h"
144 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
186 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
188 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
189 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
190 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
191 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
193 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
194 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
195 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
214 SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
300 return "Cell SPU DAG->DAG Pattern Instruction Selection";
333 report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
581 return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32);
584 return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32);
587 return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
590 return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32);
593 return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
596 return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32);
604 return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
633 NewOpc = SPU::AIr32;
638 NewOpc = SPU::Ar32;
639 Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
640 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
773 unsigned Opc = SPU::ROTMAIr32_i32;
776 Opc = SPU::ROTMr32;
804 unsigned Opc = SPU::DFNMSf64;
806 Opc = SPU::DFNMSv2f64;
817 unsigned Opc = SPU::XORfneg64;
822 Opc = SPU::XORfnegvec;
833 return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
840 return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
870 && RN->getReg() != SPU::R1))) {
871 NewOpc = SPU::Ar32;
877 NewOpc = SPU::AIr32;
880 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
926 SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
927 ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
929 VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
940 CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
947 CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
953 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
957 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
961 CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
964 CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
999 CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1006 CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1012 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1016 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1021 Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1025 Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1030 CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1033 CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1064 CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1071 CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1073 CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1076 CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1090 CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1098 CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1104 CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1108 CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1111 CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1132 SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1199 /// SPU-specific DAG, ready for instruction scheduling.
