Lines Matching refs:SPU
1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
103 // Set RTLIB libcall names as used by SPU:
106 // Set up the SPU's register classes:
107 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
109 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
110 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
111 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
112 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
113 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
115 // SPU has no sign or zero extended loads for i1, i8, i16:
130 // SPU constant load actions are custom lowered:
134 // SPU's loads and stores have to be custom lowered:
175 // SPU has no intrinsics for these particular operations:
178 // SPU has no division/remainder instructions
229 // SPU can do rotate right and left, so legalize it... but customize for i8
242 // SPU has no native version of shift left/right for i8
282 // SPU does not have BSWAP. It does have i32 support CTLZ.
305 // SPU has a version of select that implements (a&~c)|(b&c), just like
328 // SPU has a legal FP -> signed INT instruction for f32, but for f64, need
337 // FDIV on SPU requires custom lowering
340 // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
381 // Cell SPU has instructions for converting between i64 and fp.
393 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
394 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
395 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
396 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
397 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
398 addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
442 setStackPointerRegisterToSaveRestore(SPU::R1);
497 // Return the Cell SPU's SETCC result type
622 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
631 // creating a 0(reg) d-form address due to the SPU's block loads.
816 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
825 // creating a 0(reg) d-form address due to the SPU's block loads.
1020 SPU::LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM) {
1142 ArgRegClass = &SPU::R8CRegClass;
1145 ArgRegClass = &SPU::R16CRegClass;
1148 ArgRegClass = &SPU::R32CRegClass;
1151 ArgRegClass = &SPU::R64CRegClass;
1154 ArgRegClass = &SPU::GPRCRegClass;
1157 ArgRegClass = &SPU::R32FPRegClass;
1160 ArgRegClass = &SPU::R64FPRegClass;
1168 ArgRegClass = &SPU::VECREGRegClass;
1197 SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
1198 SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
1199 SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
1200 SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
1201 SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
1202 SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
1203 SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
1204 SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
1205 SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
1206 SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
1207 SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
1220 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass);
1283 SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
1332 // linkage area, and parameter passing area. According to the SPU ABI,
1515 SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
1537 SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
1560 SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
1586 SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
1605 SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
1619 SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
1628 SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
1643 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerBUILD_VECTOR");
1707 return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
1717 SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
1907 DAG.getRegister(SPU::R1, PtrVT),
2000 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
2002 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
2004 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
2006 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
2170 DAG.getRegister(SPU::R1, PtrVT),
2314 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerByteImmed");
2342 operand. SPU has such an instruction, but it counts the number of
2368 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
2400 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2401 unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2628 ISD::SELECT_CC can (generally) be implemented directly on the SPU using the
2754 SPU::GPRCRegClass.getID(),
3064 DEBUG(errs() << "\nReplace.SPU: ");
3139 return std::make_pair(0U, SPU::R64CRegisterClass);
3140 return std::make_pair(0U, SPU::R32CRegisterClass);
3143 return std::make_pair(0U, SPU::R32FPRegisterClass);
3145 return std::make_pair(0U, SPU::R64FPRegisterClass);
3148 return std::make_pair(0U, SPU::GPRCRegisterClass);
3155 //! Compute used/known bits for a SPU operand
3220 // SPU's addresses are 256K:
3230 // The SPU target isn't yet aware of offsets.
