Lines Matching refs:SPU
1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
35 return (opc == SPU::BR
36 || opc == SPU::BRA
37 || opc == SPU::BI);
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
46 || opc == SPU::BRZr32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr16
49 || opc == SPU::BRHNZv8i16
50 || opc == SPU::BRHZr16
51 || opc == SPU::BRHZv8i16);
56 : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
76 case SPU::LQDv16i8:
77 case SPU::LQDv8i16:
78 case SPU::LQDv4i32:
79 case SPU::LQDv4f32:
80 case SPU::LQDv2f64:
81 case SPU::LQDr128:
82 case SPU::LQDr64:
83 case SPU::LQDr32:
84 case SPU::LQDr16: {
102 case SPU::STQDv16i8:
103 case SPU::STQDv8i16:
104 case SPU::STQDv4i32:
105 case SPU::STQDv4f32:
106 case SPU::STQDv2f64:
107 case SPU::STQDr128:
108 case SPU::STQDr64:
109 case SPU::STQDr32:
110 case SPU::STQDr16:
111 case SPU::STQDr8: {
134 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
147 if (RC == SPU::GPRCRegisterClass) {
148 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
149 } else if (RC == SPU::R64CRegisterClass) {
150 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
151 } else if (RC == SPU::R64FPRegisterClass) {
152 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
153 } else if (RC == SPU::R32CRegisterClass) {
154 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
155 } else if (RC == SPU::R32FPRegisterClass) {
156 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
157 } else if (RC == SPU::R16CRegisterClass) {
158 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
159 } else if (RC == SPU::R8CRegisterClass) {
160 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
161 } else if (RC == SPU::VECREGRegisterClass) {
162 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
182 if (RC == SPU::GPRCRegisterClass) {
183 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
184 } else if (RC == SPU::R64CRegisterClass) {
185 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
186 } else if (RC == SPU::R64FPRegisterClass) {
187 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
188 } else if (RC == SPU::R32CRegisterClass) {
189 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
190 } else if (RC == SPU::R32FPRegisterClass) {
191 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
192 } else if (RC == SPU::R16CRegisterClass) {
193 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
194 } else if (RC == SPU::R8CRegisterClass) {
195 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
196 } else if (RC == SPU::VECREGRegisterClass) {
197 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
290 if (I->getOpcode() == SPU::HBRA ||
291 I->getOpcode() == SPU::HBR_LABEL){
356 "SPU branch conditions have two components!");
366 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
372 MIB = BuildMI(&MBB, DL, get(SPU::BR));
380 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
390 MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
401 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
408 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
431 { SPU::BRNZr32, SPU::BRZr32 },
432 { SPU::BRNZv4i32, SPU::BRZv4i32 },
433 { SPU::BRZr32, SPU::BRNZr32 },
434 { SPU::BRZv4i32, SPU::BRNZv4i32 },
435 { SPU::BRHNZr16, SPU::BRHZr16 },
436 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
437 { SPU::BRHZr16, SPU::BRHNZr16 },
438 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
442 // Pretty dull mapping between the two conditions that SPU can generate:
