Lines Matching defs:loop
252 // simple loop. The incoming instruction knows the destination vreg to
262 // loop:
265 // bneid samt, loop
270 MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
272 F->insert(It, loop);
284 MBB->addSuccessor(loop);
287 // Next, add the finish block as a successor of the loop block
288 loop->addSuccessor(finish);
289 loop->addSuccessor(loop);
307 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
309 .addReg(NDST).addMBB(loop);
313 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
315 .addReg(NAMT).addMBB(loop);
318 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
320 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
322 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
326 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
330 BuildMI(loop, dl, TII->get(MBlaze::BNEID))
332 .addMBB(loop);
337 .addReg(NDST).addMBB(loop);
432 loop. The incoming instruction knows the destination vreg to
442 // loop:
445 // bneid samt, loop
