Lines Matching full:mblaze
1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a
15 #define DEBUG_TYPE "mblaze-lower"
59 // MBlaze does not have i1 type, so use i32 for
64 addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
66 addRegisterClass(MVT::f32, MBlaze::GPRRegisterClass);
99 // MBlaze has no REM or DIVREM operations.
131 // MBlaze doesn't have MUL_LOHI
145 // MBlaze Custom Operations
158 // Operations not directly supported by MBlaze.
180 // MBlaze doesn't have extending float->double load/store
186 setStackPointerRegisterToSaveRestore(MBlaze::R1);
218 case MBlaze::ShiftRL:
219 case MBlaze::ShiftRA:
220 case MBlaze::ShiftL:
223 case MBlaze::Select_FCC:
224 case MBlaze::Select_CC:
227 case MBlaze::CAS32:
228 case MBlaze::SWP32:
229 case MBlaze::LAA32:
230 case MBlaze::LAS32:
231 case MBlaze::LAD32:
232 case MBlaze::LAO32:
233 case MBlaze::LAX32:
234 case MBlaze::LAN32:
237 case MBlaze::MEMBARRIER:
291 unsigned IAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
292 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
296 unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
297 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL)
301 BuildMI(MBB, dl, TII->get(MBlaze::BEQID))
305 unsigned DST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
306 unsigned NDST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
307 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
311 unsigned SAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
312 unsigned NAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
313 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
317 if (MI->getOpcode() == MBlaze::ShiftL)
318 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
319 else if (MI->getOpcode() == MBlaze::ShiftRA)
320 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
321 else if (MI->getOpcode() == MBlaze::ShiftRL)
322 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
326 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
330 BuildMI(loop, dl, TII->get(MBlaze::BNEID))
335 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
371 case MBlazeCC::EQ: Opc = MBlaze::BEQID; break;
372 case MBlazeCC::NE: Opc = MBlaze::BNEID; break;
373 case MBlazeCC::GT: Opc = MBlaze::BGTID; break;
374 case MBlazeCC::LT: Opc = MBlaze::BLTID; break;
375 case MBlazeCC::GE: Opc = MBlaze::BGEID; break;
376 case MBlazeCC::LE: Opc = MBlaze::BLEID; break;
399 //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
404 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
467 BuildMI(start, dl, TII->get(MBlaze::LWX), MI->getOperand(0).getReg())
469 .addReg(MBlaze::R0);
477 case MBlaze::SWP32:
483 case MBlaze::LAN32:
484 case MBlaze::LAX32:
485 case MBlaze::LAO32:
486 case MBlaze::LAD32:
487 case MBlaze::LAS32:
488 case MBlaze::LAA32: {
492 case MBlaze::LAA32: opcode = MBlaze::ADDIK; break;
493 case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break;
494 case MBlaze::LAD32: opcode = MBlaze::AND; break;
495 case MBlaze::LAO32: opcode = MBlaze::OR; break;
496 case MBlaze::LAX32: opcode = MBlaze::XOR; break;
497 case MBlaze::LAN32: opcode = MBlaze::AND; break;
500 finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
508 if (MI->getOpcode() == MBlaze::LAN32) {
510 finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
511 BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg)
518 case MBlaze::CAS32: {
528 unsigned CMP = R.createVirtualRegister(MBlaze::GPRRegisterClass);
529 BuildMI(start, dl, TII->get(MBlaze::CMP), CMP)
533 BuildMI(start, dl, TII->get(MBlaze::BNEID))
543 unsigned CHK = R.createVirtualRegister(MBlaze::GPRRegisterClass);
544 BuildMI(final, dl, TII->get(MBlaze::SWX))
547 .addReg(MBlaze::R0);
549 BuildMI(final, dl, TII->get(MBlaze::ADDIC), CHK)
550 .addReg(MBlaze::R0)
553 BuildMI(final, dl, TII->get(MBlaze::BNEID))
659 MBlaze::R5, MBlaze::R6, MBlaze::R7,
660 MBlaze::R8, MBlaze::R9, MBlaze::R10
689 // MBlaze does not yet support tail call optimization
692 // The MBlaze requires stack slots for arguments passed to var arg
900 RC = MBlaze::GPRRegisterClass;
902 RC = MBlaze::GPRRegisterClass;
964 // The last register argument that must be saved is MBlaze::R10
965 TargetRegisterClass *RC = MBlaze::GPRRegisterClass;
967 unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5);
969 unsigned End = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R10);
1049 unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14
1050 : MBlaze::R15;
1060 // MBlaze Inline Assembly Support
1068 // MBlaze specific constrainy
1126 return std::make_pair(0U, MBlaze::GPRRegisterClass);
1133 return std::make_pair(0U, MBlaze::GPRRegisterClass);
1141 // The MBlaze target isn't yet aware of offsets.
