Lines Matching full:operand
17 // source operands or one register source operand and one immediate operand.
26 , 1 // first operand read after one cycle
27 , 1 ]>, // second operand read after one cycle
30 // register source operands or one register source operand and one immediate
31 // operand. The instruction takes one cycle to execute in each of the
40 , 1 // first operand read after one cycle
41 , 1 ]>, // second operand read after one cycle
53 , 1 // first operand read after one cycle
54 , 1 ]>, // second operand read after one cycle
57 // source operands or one register source operand and one immediate operand.
67 , 1 // first operand read after one cycle
68 , 1 ]>, // second operand read after one cycle
70 // Branch instruction with one source operand register. The instruction takes
71 // one cycle to execute in each of the pipeline stages. The source operand is
77 [ 1 ]>, // first operand read after one cycle
79 // Conditional branch instruction with two source operand registers. The
86 [ 1 // first operand read after one cycle
87 , 1 ]>, // second operand read after one cycle
90 // operand register. The instruction takes one cycle to execute in each of
91 // the pipeline stages. The source operand is read during the decode stage
98 , 1 ]>, // first operand read after one cycle
100 // Cache control instruction with two source operand registers. The
108 [ 1 // first operand read after one cycle
109 , 1 ]>, // second operand read after one cycle
112 // operand registers. The instruction takes one cycle to execute in each of
121 , 1 // first operand read after one cycle
122 , 1 ]>, // second operand read after one cycle
125 // source operand registers. The instruction takes one cycle to execute in
134 , 1 // first operand read after one cycle
135 , 1 ]>, // second operand read after one cycle
138 // register and one source operand register. The instruction takes one cycle
147 , 1 ]>, // first operand read after one cycle
150 // register and one source operand register. The instruction takes one cycle
159 , 1 ]>, // first operand read after one cycle
162 // one source operand register. The instruction takes one cycle to execute in
171 , 1 ]>, // first operand read after one cycle
174 // two source operand registers. The instruction takes one cycle to execute
183 , 1 // first operand read after one cycle
184 , 1 ]>, // second operand read after one cycle
186 // FSL get instruction with one register or immediate source operand and one
189 // The one source operand is read during the decode stage and the result is
196 , 1 ]>, // first operand read after one cycle
199 // register source operand and one immediate operand. There is no result
207 [ 1 // first operand read after one cycle
208 , 1 ]>, // second operand read after one cycle
211 // register source operands and one immediate operand. There is no result
219 [ 1 // first operand read after one cycle
220 , 1 // second operand read after one cycle
221 , 1 ]>, // third operand read after one cycle
224 // register source operands or one register source operand and one immediate
225 // operand. The instruction takes one cycle to execute in each of the
234 , 1 // second operand read after one cycle
235 , 1 ]> // third operand read after one cycle
