Lines Matching refs:PPC
1 //=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
42 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
44 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
45 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
59 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
71 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
87 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
270 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
313 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
316 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
317 .addReg(PPC::X31)
319 .addReg(PPC::X1);
322 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
323 .addReg(PPC::X0)
325 .addReg(PPC::X1);
328 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
331 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
332 .addReg(PPC::R31)
334 .addReg(PPC::R1);
337 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
338 .addReg(PPC::R0)
340 .addReg(PPC::R1);
359 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
360 .addReg(PPC::R1)
364 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
365 .addReg(PPC::R0, RegState::Kill)
367 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
368 .addReg(PPC::R1)
369 .addReg(PPC::R1)
370 .addReg(PPC::R0);
372 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
373 .addReg(PPC::R1)
375 .addReg(PPC::R1);
377 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
380 .addReg(PPC::R0, RegState::Kill)
382 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
383 .addReg(PPC::R1)
384 .addReg(PPC::R1)
385 .addReg(PPC::R0);
393 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
394 .addReg(PPC::X1)
397 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
398 .addReg(PPC::X0)
400 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
401 .addReg(PPC::X1)
402 .addReg(PPC::X1)
403 .addReg(PPC::X0);
405 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
406 .addReg(PPC::X1)
408 .addReg(PPC::X1);
410 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
412 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
413 .addReg(PPC::X0, RegState::Kill)
415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
416 .addReg(PPC::X1)
417 .addReg(PPC::X1)
418 .addReg(PPC::X0);
429 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
437 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
443 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
449 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
459 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
460 .addReg(PPC::R1)
461 .addReg(PPC::R1);
463 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
464 .addReg(PPC::X1)
465 .addReg(PPC::X1);
472 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
474 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
475 (isPPC64 ? PPC::X1 : PPC::R1));
489 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
493 if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ)
495 if (Reg == PPC::CR2UN)
496 Reg = PPC::CR2;
515 assert((RetOpcode == PPC::BLR ||
516 RetOpcode == PPC::TCRETURNri ||
517 RetOpcode == PPC::TCRETURNdi ||
518 RetOpcode == PPC::TCRETURNai ||
519 RetOpcode == PPC::TCRETURNri8 ||
520 RetOpcode == PPC::TCRETURNdi8 ||
521 RetOpcode == PPC::TCRETURNai8) &&
556 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
557 RetOpcode == PPC::TCRETURNdi ||
558 RetOpcode == PPC::TCRETURNai ||
559 RetOpcode == PPC::TCRETURNri8 ||
560 RetOpcode == PPC::TCRETURNdi8 ||
561 RetOpcode == PPC::TCRETURNai8;
587 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
588 .addReg(PPC::R31).addImm(FrameSize);
590 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
592 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
593 .addReg(PPC::R0, RegState::Kill)
595 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
596 .addReg(PPC::R1)
597 .addReg(PPC::R31)
598 .addReg(PPC::R0);
602 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
603 .addReg(PPC::R1).addImm(FrameSize);
605 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
606 .addImm(0).addReg(PPC::R1);
611 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
612 .addReg(PPC::X31).addImm(FrameSize);
614 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
616 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
617 .addReg(PPC::X0, RegState::Kill)
619 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
620 .addReg(PPC::X1)
621 .addReg(PPC::X31)
622 .addReg(PPC::X0);
625 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
626 .addReg(PPC::X1).addImm(FrameSize);
628 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
629 .addImm(0).addReg(PPC::X1);
636 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
637 .addImm(LROffset/4).addReg(PPC::X1);
640 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
641 .addImm(FPOffset/4).addReg(PPC::X1);
644 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
647 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
648 .addImm(LROffset).addReg(PPC::R1);
651 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
652 .addImm(FPOffset).addReg(PPC::R1);
655 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
660 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
664 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
665 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
666 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
667 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
668 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
669 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
670 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
686 } else if (RetOpcode == PPC::TCRETURNdi) {
689 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
691 } else if (RetOpcode == PPC::TCRETURNri) {
694 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
695 } else if (RetOpcode == PPC::TCRETURNai) {
698 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
699 } else if (RetOpcode == PPC::TCRETURNdi8) {
702 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
704 } else if (RetOpcode == PPC::TCRETURNri8) {
707 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
708 } else if (RetOpcode == PPC::TCRETURNai8) {
711 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
776 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
777 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
800 unsigned MinGPR = PPC::R31;
801 unsigned MinG8R = PPC::X31;
802 unsigned MinFPR = PPC::F31;
803 unsigned MinVR = PPC::V31;
819 if (PPC::GPRCRegisterClass->contains(Reg)) {
827 } else if (PPC::G8RCRegisterClass->contains(Reg)) {
835 } else if (PPC::F8RCRegisterClass->contains(Reg)) {
844 } else if (PPC::CRBITRCRegisterClass->contains(Reg)
845 || PPC::CRRCRegisterClass->contains(Reg)) {
847 } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
849 } else if (PPC::VRRCRegisterClass->contains(Reg)) {
933 if (PPC::CRBITRCRegisterClass->contains(Reg) ||
934 PPC::CRRCRegisterClass->contains(Reg)) {
951 if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
