Lines Matching refs:R0
328 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
338 .addReg(PPC::R0)
359 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
364 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
365 .addReg(PPC::R0, RegState::Kill)
370 .addReg(PPC::R0);
377 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
380 .addReg(PPC::R0, RegState::Kill)
385 .addReg(PPC::R0);
590 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
592 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
593 .addReg(PPC::R0, RegState::Kill)
598 .addReg(PPC::R0);
647 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
655 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
666 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
772 // r0 for now.
