Lines Matching full:unitsize
530 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
534 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
537 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
538 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
539 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
540 LHSStart+j+i*UnitSize) ||
541 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
542 RHSStart+j+i*UnitSize))
550 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
553 return isVMerge(N, UnitSize, 8, 24);
554 return isVMerge(N, UnitSize, 8, 8);
559 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
562 return isVMerge(N, UnitSize, 0, 16);
563 return isVMerge(N, UnitSize, 0, 0);
