Lines Matching defs:Reg
120 unsigned Reg = MO.getReg();
121 if (!Reg)
123 for (const unsigned *AsI = TRI.getOverlaps(Reg); *AsI; ++AsI)
157 unsigned Reg = isSub
160 if (Reg) {
165 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
275 unsigned Reg = II->first;
277 if (Reg == X86::EAX || Reg == X86::AX ||
278 Reg == X86::AH || Reg == X86::AL)
317 unsigned Reg = I->getReg();
340 if (HasFP && FramePtr == Reg)
344 MachineLocation CSSrc(Reg);
433 // REG < 64 => DW_CFA_offset + Reg
903 unsigned Reg = CSI[i-1].getReg();
904 if (!X86::GR64RegClass.contains(Reg) &&
905 !X86::GR32RegClass.contains(Reg))
908 MBB.addLiveIn(Reg);
909 if (Reg == FPReg)
913 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
923 unsigned Reg = CSI[i-1].getReg();
924 if (X86::GR64RegClass.contains(Reg) ||
925 X86::GR32RegClass.contains(Reg))
928 MBB.addLiveIn(Reg);
929 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
930 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
951 unsigned Reg = CSI[i].getReg();
952 if (X86::GR64RegClass.contains(Reg) ||
953 X86::GR32RegClass.contains(Reg))
955 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
956 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
964 unsigned Reg = CSI[i].getReg();
965 if (!X86::GR64RegClass.contains(Reg) &&
966 !X86::GR32RegClass.contains(Reg))
968 if (Reg == FPReg)
971 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1147 unsigned Reg = Src.getReg();
1157 } else if (Reg < 64) {
1158 // DW_CFA_offset + Reg
1160 int CURegNum = TRI->getCompactUnwindRegNum(Reg, IsEH);
1182 unsigned Reg = SavedRegs[I];
1183 if (Reg == unsigned(FramePointerReg)) continue;
1184 Encoding |= (Reg & 0x7) << (I * 3); // Register encoding
