Lines Matching defs:SetCC
223 // X86 is weird, it always uses i8 for shift amounts and setcc results.
453 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
454 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
455 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
456 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
457 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
458 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
461 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
7336 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7341 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
7380 User->getOpcode() != ISD::SETCC &&
7508 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7516 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7542 // If the input is a setcc, then reuse the input setcc or use a new one with
7544 if (Op0.getOpcode() == X86ISD::SETCC) {
7551 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7562 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7722 if (Cond.getOpcode() == ISD::SETCC) {
7732 if (Cond.getOpcode() == X86ISD::SETCC &&
7770 // setting operand in place of the X86ISD::SETCC.
7771 if (Cond.getOpcode() == X86ISD::SETCC ||
7838 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7844 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7846 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7850 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7851 // 1 and that the SETCC node has a single use.
7857 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7871 if (Cond.getOpcode() == ISD::SETCC) {
7894 // setting operand in place of the X86ISD::SETCC.
7895 if (Cond.getOpcode() == X86ISD::SETCC ||
7971 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8291 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8293 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8297 // or testp pattern and a setcc for the result.
8357 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
8358 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9003 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9004 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9055 SDValue SetCC =
9056 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9060 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
9069 SDValue SetCC =
9070 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9074 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
9320 case ISD::SETCC: return LowerSETCC(Op, DAG);
9508 case X86ISD::SETCC: return "X86ISD::SETCC";
11073 case X86ISD::SETCC:
11227 Cond.getOpcode() == ISD::SETCC) {
11376 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
11398 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
11496 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
11500 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11514 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
11517 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11555 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11789 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12239 // ISD::SETCC is always legalized to i8.
12261 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
12337 SDValue SetCC = Ext.getOperand(0);
12338 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
12341 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
12345 SDValue Cmp = SetCC.getOperand(1);
12391 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
