Lines Matching refs:SRA
481 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
737 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
976 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
977 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1098 setTargetDAGCombine(ISD::SRA);
6701 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6711 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8881 // Optimize shl/srl/sra with constant shift amount.
8917 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
8922 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9340 case ISD::SRA:
11760 case ISD::SRA:
11949 // Validate that the Mask operand is a vector sra node. The sra node
11963 // Check that the SRA is all signbits.
12379 case ISD::SRA:
