Lines Matching refs:Cycles
19 0x01 cycles_div_busy Cycles the divider is busy
58 0x01 l1d_l2 Cycles L1D and L2 locked
59 0x02 l1d Cycles L1D locked
61 0x00 thread_p Cycles when thread is not halted (programmable counter)
62 0x01 ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
66 0x04 walk_cycles DTLB load miss page walk cycles
73 0x04 walk_cycles DTLB miss page walk cycles
95 0x01 lcp Length Change Prefix stall cycles
96 0x02 mru Stall cycles due to BPU MRU bypass
97 0x04 iq_full Instruction Queue full stall cycles
98 0x08 regen Regen stall cycles
99 0x0f any Any Instruction Length Decoder stall cycles
107 0x04 walk_cycles ITLB miss page walk cycles
128 0x04 cycles_stalled L1I instruction fetch stall cycles
196 0x01 cycles Cycles machine clear asserted
231 0x01 flags Flag stall cycles
232 0x02 registers Partial register stall cycles
233 0x04 rob_read_port ROB read port stalls cycles
234 0x08 scoreboard Scoreboard stall cycles
235 0x0f any All RAT stall cycles
237 0x01 any Resource related stall cycles
238 0x02 load Load buffer stall cycles
239 0x04 rs_full Reservation Station full stall cycles
240 0x08 store Store buffer stall cycles
241 0x10 rob_full ROB full stall cycles
242 0x20 fpcw FPU control word write stall cycles
243 0x40 mxcsr MXCSR rename stall cycles
244 0x80 other Other Resource related stall cycles
286 0x01 stall_cycles Cycles no Uops are decoded
296 0x1f core_active_cycles_no_port5 Cycles Uops executed on ports 0-4 (core count)
298 0x3f core_active_cycles Cycles Uops executed on any port (core count)
305 0x01 active_cycles Cycles Uops are being retired
