Lines Matching refs:TO
62 /* One bit flags for the opcode. These are used to indicate which
97 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
169 /* A macro to extract the major opcode from an instruction. */
181 -1 to indicate that BITM and SHIFT cannot be used to determine
185 /* Insertion function. This is used by the assembler. To insert an
190 (i is the instruction which we are filling in, o is a pointer to
196 the operand value is illegal, *ERRMSG will be set to a warning
203 /* Extraction function. This is used by the disassembler. To
210 (i is the instruction, o is a pointer to this structure, and op
215 the INVALID argument is not NULL, *INVALID will be set to
238 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
243 is used to support extended mnemonics such as mr, for which two
252 store instructions which want their operands to look like
266 /* This operand names a register. The disassembler uses this to print
334 /* One bit flags for the opcode. These are used to indicate which
339 /* A format string to turn the macro into a normal instruction.
371 permits the disassembler to use them, and simplifies the assembler
373 strictly constant data, so the compiler should be able to put it in
424 We used to put parens around the various additions, like the one
433 /* The zero index is used to indicate the end of the list of
461 forced to zero. */
572 lower four bits are forced to zero. */
578 lower two bits are forced to zero. */
644 forced to zero. */
663 operand which is a bitmask indicating which bits to select. This
671 bit is wrapped to the low end. */
811 /* The TO field in a D or X form instruction. */
812 #define TO TBR + 1
817 #define UI TO + 1
902 /* The functions used to insert and extract complicated operands. */
955 This modifier means that the branch is not expected to be taken.
956 For chips built to versions of the architecture prior to version 2
957 (ie. not Power4 compatible), we set the y bit of the BO field to 1
960 we just want to print the normal form of the instruction.
1013 This is like BDM, above, except that the branch is expected to be
1065 /* Certain encodings have bits that are required to be zero.
1096 /* Certain encodings have bits that are required to be zero.
1116 /* The BO field in a B form instruction. Warn about attempts to set
1117 the field to an illegal value. */
1145 extracting it, we force it to be even. */
1156 *errmsg = _("attempt to set y bit when using + or - modifier");
1193 /* If the optional field on mfcr is missing that means we want to use
1195 case we'll have VALUE zero. There doesn't seem to be a way to
1248 marks it as invalid, since we never want to recognize an
1335 is wrapped to the low end. */
1372 invalid, since we never want to recognize an instruction which uses
1594 /* Macros used to form opcodes. */
1600 /* The main opcode combined with a trap code in the TO field of a D
1603 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1791 /* An X form trap instruction with the TO field specified. */
1792 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1820 /* An XL form instruction with the LK field set to 0. */
1936 /* The TO encodings used in extended trap mnemonics. */
2004 MASK is the opcode mask; this is used to tell the disassembler
2010 instruction which matches, so this table is sorted to put more
2030 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
3433 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3434 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3551 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
5036 extracting x bits from some word you want to use just 32-x, because
5094 /* Determine which set of machines to disassemble for. PPC403/601 or
5335 the instruction to be valid. */
