Cross Reference: /external/v8/src/mips/assembler-mips.cc

Lines Matching refs:ORI
146   // specially coded on MIPS means that it is a lui/ori instruction, and that is
1183 void Assembler::ori(Register rt, Register rs, int32_t j) {
1184   GenInstrImmediate(ORI, rs, rt, j);
1268   ori(at, at, src.offset_ & kImm16Mask);  // Load 32-bit offset.
2021   ASSERT(((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) ||
2023                             (instr2 & kOpcodeMask) == ORI ||
2029     } else if ((instr2 & kOpcodeMask) == ORI) {
2034   } else if ((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) {
2055   CHECK(((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) ||
2057                            (instr2 & kOpcodeMask)== ORI ||
2072     // ori rt zero_reg j.
2074     *(p+1) = ORI | rt_code | (itarget & kImm16Mask);
2082     // ori rt rt, (kImm16Mask & itarget).
2084     *(p+1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
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