Lines Matching refs:zero_reg
81 0, // zero_reg
121 zero_reg,
405 // nop(type) == sll(zero_reg, zero_reg, type);
410 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
411 rs == static_cast<uint32_t>(ToNumber(zero_reg)) &&
872 beq(zero_reg, zero_reg, offset);
878 bgezal(zero_reg, offset);
906 GenInstrImmediate(BGTZ, rs, zero_reg, offset);
913 GenInstrImmediate(BLEZ, rs, zero_reg, offset);
951 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
966 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1025 or_(reg_popped, reg_pushed, zero_reg);
1108 or_(reg_popped, reg_pushed, zero_reg); // Move instruction.
1115 or_(reg_popped, reg_pushed, zero_reg); // Move instruction.
1123 or_(reg_popped, reg_pushed, zero_reg); // Move instruction.
1147 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
1152 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
1157 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
1162 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
1208 // Don't allow nop instructions in the form sll zero_reg, zero_reg to be
1212 ASSERT(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
1213 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
1223 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
1233 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
1361 or_(reg_loaded, reg_stored, zero_reg); // Move instruction.
1439 GenInstrImmediate(LUI, zero_reg, rd, j);
1505 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
1510 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
1832 mtc1(zero_reg, f14);
2067 // addiu rt zero_reg j.
2072 // ori rt zero_reg j.
