Lines Matching full:rounding
49 * FP rounding mode observed only for float->int conversions and
51 float-to-float rounding. For all other operations,
4535 /* --------- Get/put the FPU rounding mode. --------- */
4548 /* --------- Synthesise a 2-bit FPU rounding mode. --------- */
5066 rounding mode. Therefore, pass the 16-bit value
8577 /* Get the current SSE rounding mode. */
9532 I32 in mmx, according to prevailing SSE rounding mode */
9534 I32 in mmx, rounding towards zero */
9589 according to prevailing SSE rounding mode
9591 according to prevailing SSE rounding mode
9671 /* The only thing we observe in %mxcsr is the rounding mode.
10035 /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
10045 /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
10652 lo half xmm(G), and zero upper half, rounding towards zero */
10654 lo half xmm(G), according to prevailing rounding mode, and zero
10708 I32 in mmx, according to prevailing SSE rounding mode */
10710 I32 in mmx, rounding towards zero */
10760 lo half xmm(G), rounding according to prevailing SSE rounding
10847 xmm(G), rounding towards zero */
10849 xmm(G), as per the prevailing rounding mode */
10932 according to prevailing SSE rounding mode
10934 according to prevailing SSE rounding mode
10984 low 1/4 xmm(G), according to prevailing SSE rounding mode */
15425 /* (imm & 3) contains an Intel-encoded rounding mode. Because
15427 we can use that value directly in the IR as a rounding
15482 /* (imm & 3) contains an Intel-encoded rounding mode. Because
15484 we can use that value directly in the IR as a rounding
15549 /* (imm & 3) contains an Intel-encoded rounding mode. Because
15551 rounding
