Lines Matching defs:rN
2340 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12,
2343 vassert(rN < 16);
2347 DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12);
2350 getIRegA(rN),
2359 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
2363 vassert(rN < 16);
2374 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5);
2384 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2396 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2407 DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM);
2415 DIS(buf, "[r%u, %cr%u, ROR #%u]", rN, opChar, rM, imm5);
2423 getIRegA(rN), index);
2429 IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8,
2432 vassert(rN < 16);
2436 DIS(buf, "[r%u, #%c%u]", rN, opChar, imm8);
2439 getIRegA(rN),
2446 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
2449 vassert(rN < 16);
2454 DIS(buf, "[r%u, %c r%u]", rN, opChar, rM);
2456 getIRegA(rN), index);
7922 UInt rN = INSN(19,16);
7940 assign(initialRn, isT ? getIRegT(rN) : getIRegA(rN));
7978 DIP("}, [r%u]", rN);
8074 DIP("}, [r%u]", rN);
8088 putIRegT(rN, e, IRTemp_INVALID);
8090 putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
8096 putIRegT(rN, e, IRTemp_INVALID);
8098 putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
8167 putIRegT(rN, e, IRTemp_INVALID);
8169 putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
8175 putIRegT(rN, e, IRTemp_INVALID);
8177 putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
8193 DIP("}, [r%u]", rN);
8395 /* ------------ smulwb<y><c> <Rd>,<Rn>,<Rm> ------------- */
8396 /* ------------ smulwt<y><c> <Rd>,<Rn>,<Rm> ------------- */
8456 /* ------------ pkhbt<c> Rd, Rn, Rm {,LSL #imm} ------------- */
8457 /* ------------ pkhtb<c> Rd, Rn, Rm {,ASR #imm} ------------- */
8517 /* ---------- usat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
8575 /* ----------- ssat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
8633 /* -------------- usat16<c> <Rd>,#<imm4>,<Rn> --------------- */
8694 /* -------------- uadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8743 /* -------------- sadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8793 /* ---------------- usub16<c> <Rd>,<Rn>,<Rm> ---------------- */
8843 /* -------------- ssub16<c> <Rd>,<Rn>,<Rm> -------------- */
8893 /* ----------------- uadd8<c> <Rd>,<Rn>,<Rm> ---------------- */
8942 /* ------------------- sadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
8992 /* ------------------- usub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9042 /* ------------------- ssub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9092 /* ------------------ qadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9137 /* ------------------ qsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
9182 /* ------------------ uqadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9227 /* ------------------ uqsub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9272 /* ----------------- uhadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9317 /* ----------------- shadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9362 /* ------------------ qadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
9407 /* ------------------ qsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
9458 /* ------------------- qsax<c> <Rd>,<Rn>,<Rm> ------------------- */
9529 /* ------------------- qasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9597 /* ------------------- sasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9671 /* --------------- smuad, smuadx<c><Rd>,<Rn>,<Rm> --------------- */
9672 /* --------------- smsad, smsadx<c><Rd>,<Rn>,<Rm> --------------- */
9750 /* --------------- smlad{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9751 /* --------------- smlsd{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9841 /* ----- smlabb, smlabt, smlatb, smlatt <Rd>,<Rn>,<Rm>,<Ra> ----- */
9911 /* ----- smlawb, smlawt <Rd>,<Rn>,<Rm>,<Ra> ----- */
9982 /* ------------------- sel<c> <Rd>,<Rn>,<Rm> -------------------- */
10070 /* ----------------- uxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
10133 /* --------------- usad8 Rd,Rn,Rm ---------------- */
10134 /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */
10136 UInt rD = 99, rN = 99, rM = 99, rA = 99;
10141 rN = INSNT0(3,0);
10145 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13)
10154 rN = INSNA(3,0);
10155 if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */)
10162 IRExpr* rNe = isT ? getIRegT(rN) : getIRegA(rN);
10176 nCC(conq), rD, rN, rM );
10179 nCC(conq), rD, rN, rM, rA );
10206 UInt rN, /* base reg */
10209 UInt bW, /* 1: writeback to Rn */
10215 /* Get hold of the old Rn value. We might need to write its value
10220 updates Rn in the guest state before any transfers take place.
10221 Rn is
10225 assign(oldRnT, arm ? getIRegA(rN) : getIRegT(rN));
10240 // For xxMDA and xxMDB, update Rn first if necessary. We have
10246 // do the transfer first, and then update rN afterwards.
10255 putIRegA( rN, e, IRTemp_INVALID, Ijk_Boring );
10257 putIRegT( rN, e, IRTemp_INVALID );
10261 // in memory relative to the anchor. If the base reg (Rn) is part
10276 vassert(r != rN);
10289 if (bW == 0 && (regList & (1<<rN)) != 0) {
10294 vex_printf("\nREG_LIST_PRE: (rN=%d)\n", rN);
10302 if (xReg[i] == rN)
10357 /* if we're storing Rn, make sure we use the correct
10360 r == rN ? mkexpr(oldRnT)
10366 // do the transfer first, and then update rN afterwards.
10370 putIRegA( rN, e, IRTemp_INVALID, Ijk_Boring );
10372 putIRegT( rN, e, IRTemp_INVALID );
10440 C4-100, C5-26 1 FSTMX cond 1100 1000 Rn Dd 1011 offset
10441 C4-100, C5-28 2 FSTMIAX cond 1100 1010 Rn Dd 1011 offset
10442 C4-100, C5-30 3 FSTMDBX cond 1101 0010 Rn Dd 1011 offset
10444 C4-42, C5-26 1 FLDMX cond 1100 1001 Rn Dd 1011 offset
10445 C4-42, C5-28 2 FLDMIAX cond 1100 1011 Rn Dd 1011 offset
10446 C4-42, C5-30 3 FLDMDBX cond 1101 0011 Rn Dd 1011 offset
10450 IA/DB: Rn is changed by (4 + 8 x # regs transferred)
10453 1 at-Rn (access at Rn)
10454 2 ia-Rn (access at Rn, then Rn += 4+8n)
10455 3 db-Rn (Rn -= 4+8n, then access at Rn)
10464 UInt rN = INSN(19,16);
10482 if (rN == 15 && (summary == 2 || summary == 3 || isT))
10505 /* get the old Rn value */
10507 assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN),
10508 rN == 15));
10510 /* make a new value for Rn, post-insn */
10523 /* update Rn if necessary -- in case 3, we're moving it down, so
10528 putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
10530 putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
10543 /* update Rn if necessary -- in case 2, we're moving it up, so
10548 putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
10550 putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
10556 nm, nCC(conq), rN, dD, dD + nRegs - 1);
10559 nm, nCC(conq), rN, dD, dD + nRegs - 1);
10562 nm, nCC(conq), rN, dD, dD + nRegs - 1);
10577 C4-96, C5-26 1 FSTMD cond 1100 1000 Rn Dd 1011 offset
10578 C4-96, C5-28 2 FSTMDIA cond 1100 1010 Rn Dd 1011 offset
10579 C4-96, C5-30 3 FSTMDDB cond 1101 0010 Rn Dd 1011 offset
10581 C4-38, C5-26 1 FLDMD cond 1100 1001 Rn Dd 1011 offset
10582 C4-38, C5-28 2 FLDMIAD cond 1100 1011 Rn Dd 1011 offset
10583 C4-38, C5-30 3 FLDMDBD cond 1101 0011 Rn Dd 1011 offset
10587 IA/DB: Rn is changed by (8 x # regs transferred)
10590 1 at-Rn (access at Rn)
10591 2 ia-Rn (access at Rn, then Rn += 8n)
10592 3 db-Rn (Rn -= 8n, then access at Rn)
10601 UInt rN = INSN(19,16);
10619 if (rN == 15 && (summary == 2 || summary == 3 || isT))
10642 /* get the old Rn value */
10644 assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN),
10645 rN == 15));
10647 /* make a new value for Rn, post-insn */
10660 /* update Rn if necessary -- in case 3, we're moving it down, so
10665 putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
10667 putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
10680 /* update Rn
10685 putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
10687 putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
10693 nm, nCC(conq), rN, dD, dD + nRegs - 1);
10696 nm, nCC(conq), rN, dD, dD + nRegs - 1);
10699 nm, nCC(conq), rN, dD, dD + nRegs - 1);
10756 // VMOV dM, rD, rN
10760 UInt rN = INSN(19,16); /* hi32 */
10761 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))) {
10767 isT ? getIRegT(rN) : getIRegA(rN),
10770 DIP("vmov%s d%u, r%u, r%u\n", nCC(conq), dM, rD, rN);
10776 // VMOV rD, rN, dM
10780 UInt rN = INSN(19,16); /* hi32 */
10781 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))
10782 || rD == rN) {
10790 putIRegT(rN, hi32, condT);
10793 putIRegA(rN, hi32, condT, Ijk_Boring);
10796 DIP("vmov%s r%u, r%u, d%u\n", nCC(conq), rD, rN, dM);
10802 // VMOV sD, sD+1, rN, rM
10805 UInt rN = INSN(15,12);
10807 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
10812 unop(Iop_ReinterpI32asF32, isT ? getIRegT(rN) : getIRegA(rN)),
10818 nCC(conq), sD, sD + 1, rN, rM);
10823 // VMOV rN, rM, sD, sD+1
10826 UInt rN = INSN(15,12);
10828 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
10829 || sD == 31 || rN == rM) {
10835 putIRegT(rN, res0, condT);
10838 putIRegA(rN, res0, condT, Ijk_Boring);
10842 nCC(conq), rN, rM, sD, sD + 1);
10896 UInt rN = (INSN(7,7) << 4) | INSN(19,16);
10908 getDRegI64(rN),
10915 rT, rN, index);
10922 getDRegI64(rN),
10929 rT, rN, index);
10934 IRExpr* e = binop(Iop_GetElem32x2, getDRegI64(rN), mkU8(index));
10939 DIP("vmov%s.32 r%u, d%u[%u]\n", nCC(conq), rT, rN, index);
11037 UInt rN = INSN(19,16);
11051 align4if(isT ? getIRegT(rN) : getIRegA(rN),
11052 rN == 15),
11060 bL ? "ld" : "st", nCC(conq), dD, rN,
11325 C4-98, C5-26 1 FSTMD cond 1100 1x00 Rn Fd 1010 offset
11326 C4-98, C5-28 2 FSTMDIA cond 1100 1x10 Rn Fd 1010 offset
11327 C4-98, C5-30 3 FSTMDDB cond 1101 0x10 Rn Fd 1010 offset
11329 C4-40, C5-26 1 FLDMD cond 1100 1x01 Rn Fd 1010 offset
11330 C4-40, C5-26 2 FLDMIAD cond 1100 1x11 Rn Fd 1010 offset
11331 C4-40, C5-26 3 FLDMDBD cond 1101 0x11 Rn Fd 1010 offset
11335 IA/DB: Rn is changed by (4 x # regs transferred)
11338 1 at-Rn (access at Rn)
11339 2 ia-Rn (access at Rn, then Rn += 4n)
11340 3 db-Rn (Rn -= 4n, then access at Rn)
11350 UInt rN = INSN(19,16);
11368 if (rN == 15 && (summary == 2 || summary == 3 || isT))
11391 /* get the old Rn value */
11393 assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN),
11394 rN == 15));
11396 /* make a new value for Rn, post-insn */
11409 /* update Rn if necessary -- in case 3, we're moving it down, so
11414 putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
11416 putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
11429 /* update Rn if necessary -- in case 2, we're moving it up, so
11434 putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
11436 putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
11442 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11445 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11448 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11499 UInt rN = INSN(19,16);
11513 align4if(isT ? getIRegT(rN) : getIRegA(rN),
11514 rN == 15),
11522 bL ? "ld" : "st", nCC(conq), fD, rN,
11874 UInt rN = INSN(19,16);
11877 DIP("pld [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12);
11884 UInt rN = INSN(19,16);
11890 IRExpr* eaE = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
11907 UInt rN = INSN(19,16);
11910 DIP("pli [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12);
12153 UInt rN = (insn >> 16) & 0xF; /* 19:16 */
12166 case BITS4(0,1,0,0): /* ADD: Rd = Rn + shifter_operand */
12168 case BITS4(0,0,1,0): /* SUB: Rd = Rn - shifter_operand */
12170 case BITS4(0,0,1,1): /* RSB: Rd = shifter_operand - Rn */
12172 case BITS4(0,0,0,0): /* AND: Rd = Rn & shifter_operand */
12174 case BITS4(1,1,0,0): /* OR: Rd = Rn | shifter_operand */
12176 case BITS4(0,0,0,1): /* EOR: Rd = Rn ^ shifter_operand */
12178 case BITS4(1,1,1,0): /* BIC: Rd = Rn & ~shifter_operand */
12192 assign(rNt, getIRegA(rN));
12202 // reverse-subtract: shifter_operand - Rn
12206 // andn: shifter_operand & ~Rn
12211 // normal: Rn op shifter_operand
12254 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
12262 if (rN != 0)
12263 break; /* rN must be zero */
12294 case BITS4(1,0,1,0): /* CMP: (void) Rn - shifter_operand */
12295 case BITS4(1,0,1,1): { /* CMN: (void) Rn + shifter_operand */
12302 assign(rNt, getIRegA(rN));
12315 nCC(INSN_COND), rN, dis_buf );
12320 case BITS4(1,0,0,0): /* TST: (void) Rn & shifter_operand */
12321 case BITS4(1,0,0,1): { /* TEQ: (void) Rn ^ shifter_operand */
12328 assign(rNt, getIRegA(rN));
12346 nCC(INSN_COND), rN, dis_buf );
12351 case BITS4(0,1,0,1): /* ADC: Rd = Rn
12353 case BITS4(0,1,1,0): /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
12355 case BITS4(0,1,1,1): /* RSC: Rd = shifter_operand - Rn - (oldC ^ 1) */
12360 assign(rNt, getIRegA(rN));
12422 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
12436 A5-20 1 | 16 cond 0101 UB0L Rn Rd imm12
12437 A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm
12438 A5-24 2 | 16 cond 0101 UB1L Rn Rd imm12
12439 A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm
12440 A5-28 3 | 16 cond 0100 UB0L Rn Rd imm12
12441 A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm
12445 2 at-ea-then-upd (access at ea, then Rn = ea)
12446 3 at-Rn-then-upd (access at Rn, then Rn = ea)
12448 16 Rn +/- imm12
12449 32 Rn +/- Rm sh2 imm5
12480 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
12500 if (rN == 15) goto after_load_store_ubyte_or_word;
12501 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
12505 if (rN == 15) goto after_load_store_ubyte_or_word;
12506 if (rN == rM) goto after_load_store_ubyte_or_word;
12507 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
12527 eaE = mk_EA_reg_plusminus_imm12( rN, bU, imm12, dis_buf );
12530 eaE = mk_EA_reg_plusminus_shifted_reg( rN, bU, rM, sh2, imm5,
12538 /* get the old Rn value */
12540 assign(rnT, getIRegA(rN));
12564 /* Update Rn if necessary. */
12567 putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
12593 /* Update Rn if necessary. */
12598 vassert(rD != rN); /* since we just wrote rD */
12599 putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
12609 case 2: DIP("%sr%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
12613 case 3: DIP("%sr%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
12627 writeback, and the same register is specified for Rd and Rn,
12647 A5-36 1 | 16 cond 0001 U10L Rn Rd im4h 1SH1 im4l
12648 A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm
12649 A5-40 2 | 16 cond 0001 U11L Rn Rd im4h 1SH1 im4l
12650 A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm
12651 A5-44 3 | 16 cond 0000 U10L Rn Rd im4h 1SH1 im4l
12652 A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm
12656 2 at-ea-then-upd (access at ea, then Rn = ea)
12657 3 at-Rn-then-upd (access at Rn, then Rn = ea)
12659 16 Rn +/- imm8
12660 32 Rn +/- Rm
12692 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
12709 /* Require 11:8 == 0 for Rn +/- Rm cases */
12723 if (rN == 15) goto after_load_store_sbyte_or_hword;
12724 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
12728 if (rN == 15) goto after_load_store_sbyte_or_hword;
12729 if (rN == rM) goto after_load_store_sbyte_or_hword;
12730 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
12750 eaE = mk_EA_reg_plusminus_imm8( rN, bU, imm8, dis_buf );
12753 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
12760 /* get the old Rn value */
12762 assign(rnT, getIRegA(rN));
12801 /* Update Rn if necessary. */
12806 vassert(rD != rN); /* since we just wrote rD */
12807 putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
12814 case 2: DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
12817 case 3: DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
12830 writeback, and the same register is specified for Rd and Rn,
12848 // A5-50 LD/STMIA cond 1000 10WL Rn RegList
12849 // A5-51 LD/STMIB cond 1001 10WL Rn RegList
12850 // A5-53 LD/STMDA cond 1000 00WL Rn RegList
12851 // A5-53 LD/STMDB cond 1001 00WL Rn RegList
12858 UInt bW = (insn >> 21) & 1; /* Rn wback=1, no wback=0 */
12859 UInt rN = (insn >> 16) & 0xF;
12867 if (rN == 15) goto after_load_store_multiple;
12870 // if requested to writeback Rn, and this is a load instruction,
12871 // then Rn can't appear in RegList, since we'd have two competing
12872 // new values for Rn. We do however accept this case for store
12874 if (bW == 1 && bL == 1 && ((1 << rN) & regList) > 0)
12886 mk_ldm_stm( True/*arm*/, rN, bINC, bBEFORE, bW, bL, regList );
12891 rN, bW ? "!" : "", regList);
13097 UInt rN = INSN(15,12);
13105 if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
13116 assign( argP, getIRegA(rN));
13138 nCC(INSN_COND), rD, rM, rS, rN);
13272 UInt rN = INSN(3,0);
13275 if (rN != 15 && (write_nzcvq || write_ge)) {
13277 assign(rNt, getIRegA(rN));
13280 write_nzcvq ? "f" : "", write_ge ? "g" : "", rN);
13322 UInt rN = INSN(19,16);
13331 if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
13340 assign(tRn, getIRegA(rN));
13363 isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
13378 UInt rN = INSN(19,16);
13379 if (rT == 15 || rN == 15) {
13390 stmt( IRStmt_LLSC(Iend_LE, res, getIRegA(rN),
13393 DIP("ldrex%s r%u, [r%u]\n", nCC(INSN_COND), rT, rN);
13402 UInt rN = INSN(19,16);
13404 if (rT == 15 || rN == 15 || rD == 15
13405 || rD == rT || rD == rN) {
13418 stmt( IRStmt_LLSC(Iend_LE, resSC1, getIRegA(rN), getIRegA(rT)) );
13428 DIP("strex%s r%u, r%u, [r%u]\n", nCC(INSN_COND), rD, rT, rN);
13533 UInt rN = INSN(3,0);
13547 assign(src, rN == 15 ? mkU32(0) : getIRegA(rN));
13561 if (rN == 15) {
13566 nCC(INSN_COND), rD, rN, lsb, msb-lsb+1);
13577 UInt rN = INSN(3,0);
13582 if (rD == 15 || rN == 15 || msb >= 32) {
13592 assign(src, getIRegA(rN));
13604 nCC(INSN_COND), rD, rN, lsb, wm1 + 1);
13614 A5-36 1 | 16 cond 0001 U100 Rn Rd im4h 11S1 im4l
13615 A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
13616 A5-40 2 | 16 cond 0001 U110 Rn Rd im4h 11S1 im4l
13617 A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
13618 A5-44 3 | 16 cond 0000 U100 Rn Rd im4h 11S1 im4l
13619 A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
13623 2 at-ea-then-upd (access at ea, then Rn = ea)
13624 3 at-Rn-then-upd (access at Rn, then Rn = ea)
13626 16 Rn +/- imm8
13627 32 Rn +/- Rm
13659 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
13670 /* Require 11:8 == 0 for Rn +/- Rm cases */
13684 if (rN == 15) goto after_load_store_doubleword;
13685 if (bS == 0 && (rN == rD || rN == rD+1))
13690 if (rN == 15) goto after_load_store_doubleword;
13691 if (rN == rM) goto after_load_store_doubleword;
13692 if (bS == 0 && (rN == rD || rN == rD+1))
13713 eaE = mk_EA_reg_plusminus_imm8( rN, bU, imm8, dis_buf );
13716 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
13723 /* get the old Rn value */
13725 assign(rnT, getIRegA(rN));
13758 /* Update Rn if necessary. */
13763 vassert(rD+0 != rN); /* since we just wrote rD+0 */
13764 vassert(rD+1 != rN); /* since we just wrote rD+1 */
13766 putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
13773 case 2: DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
13776 case 3: DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
13791 UInt rN = INSN(19,16);
13796 if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
13803 assign(srcL, getIRegA(rN));
13811 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
13821 UInt rN = INSN(19,16);
13826 if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
13833 assign(srcL, getIRegA(rN));
13842 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
13886 UInt rN = INSN(3,0);
13887 if (rD != 15 && rM != 15 && rN != 15) {
13891 binop(Iop_MullS32, getIRegA(rN), getIRegA(rM)),
13895 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM);
13962 UInt rN = INSN(19,16);
13963 if ((rT & 1) == 1 || rT == BITS4(1,1,1,0) || rN == 15) {
13974 stmt( IRStmt_LLSC(Iend_LE, res, getIRegA(rN),
13979 DIP("ldrexd%s r%u, r%u, [r%u]\n", nCC(INSN_COND), rT+0, rT+1, rN);
13989 UInt rN = INSN(19,16);
13990 if (rD == 15 || (rT & 1) == 1 || rT == BITS4(1,1,1,0) || rN == 15
13991 || rD == rN || rD == rT || rD == rT+1) {
14006 stmt( IRStmt_LLSC(Iend_LE, resSC1, getIRegA(rN), mkexpr(data)) );
14016 DIP("strexd%s r%u, r%u, r%u, [r%u]\n", nCC(INSN_COND), rD, rT+0, rT+1, rN);
14573 /* ---------------- CMP Rn, Rm ---------------- */
14575 UInt rN = INSN0(2,0);
14579 assign( argL, getIRegT(rN) );
14584 DIP("%s r%u, r%u\n", isCMN ? "cmn" : "cmp", rN, rM);
14589 /* ---------------- TST Rn, Rm ---------------- */
14590 UInt rN = INSN0(2,0);
14597 assign( res, binop(Iop_And32, getIRegT(rN), getIRegT(rM)) );
14600 DIP("tst r%u, r%u\n", rN, rM);
15007 UInt rN = (h1 << 3) | INSN0(2,0);
15011 assign( argL, getIRegT(rN) );
15015 DIP("cmphi r%u, r%u\n", rN, rM);
15083 UInt rN = INSN0(2,0);
15090 getIRegT(rN), mkU32(0)) );
15100 DIP("cb%s r%u, 0x%x\n", bOP ? "nz" : "z", rN, dst - 1);
15256 /* ---------------- ADDS Rd, Rn, #uimm3 ---------------- */
15257 /* ---------------- SUBS Rd, Rn, #uimm3 ---------------- */
15259 UInt rN = INSN0(5,3);
15264 assign( argL, getIRegT(rN) );
15271 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
15277 /* ---------------- ADDS Rd, Rn, Rm ---------------- */
15278 /* ---------------- SUBS Rd, Rn, Rm ---------------- */
15280 UInt rN = INSN0(5,3);
15285 assign( argL, getIRegT(rN) );
15292 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
15298 /* ------------- LDR Rd, [Rn, Rm] ------------- */
15299 /* ------------- STR Rd, [Rn, Rm] ------------- */
15300 /* LDR/STR Rd, [Rn + Rm] */
15302 UInt rN = INSN0(5,3);
15310 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15319 DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
15325 /* ------------- LDRH Rd, [Rn, Rm] ------------- */
15326 /* ------------- STRH Rd, [Rn, Rm] ------------- */
15327 /* LDRH/STRH Rd, [Rn + Rm] */
15329 UInt rN = INSN0(5,3);
15337 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15347 DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
15352 /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
15353 /* LDRSH Rd, [Rn + Rm] */
15355 UInt rN = INSN0(5,3);
15362 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15368 DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
15373 /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
15374 /* LDRSB Rd, [Rn + Rm] */
15376 UInt rN = INSN0(5,3);
15383 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15389 DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
15395 /* ------------- LDRB Rd, [Rn, Rm] ------------- */
15396 /* ------------- STRB Rd, [Rn, Rm] ------------- */
15397 /* LDRB/STRB Rd, [Rn + Rm] */
15399 UInt rN = INSN0(5,3);
15407 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15417 DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
15433 /* ---------------- ADDS Rn, #uimm8 ---------------- */
15434 /* ---------------- SUBS Rn, #uimm8 ---------------- */
15436 UInt rN = INSN0(10,8);
15440 assign( argL, getIRegT(rN) );
15442 putIRegT( rN, binop(isSub ? Iop_Sub32 : Iop_Add32,
15446 DIP("%s r%u, #%u\n", isSub ? "subs" : "adds", rN, uimm8);
15475 /* ---------------- CMP Rn, #uimm8 ---------------- */
15476 UInt rN = INSN0(10,8);
15480 assign( argL, getIRegT(rN) );
15484 DIP("cmp r%u, #%u\n", rN, uimm8);
15489 /* -------------- (T1) MOVS Rn, #uimm8 -------------- */
15530 /* ------------- LDR Rd, [Rn, #imm5 * 4] ------------- */
15531 /* ------------- STR Rd, [Rn, #imm5 * 4] ------------- */
15532 /* LDR/STR Rd, [Rn + imm5 * 4] */
15534 UInt rN = INSN0(5,3);
15542 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5 * 4));
15551 DIP("%s r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 4);
15557 /* ------------- LDRH Rd, [Rn, #imm5 * 2] ------------- */
15558 /* ------------- STRH Rd, [Rn, #imm5 * 2] ------------- */
15559 /* LDRH/STRH Rd, [Rn + imm5 * 2] */
15561 UInt rN = INSN0(5,3);
15569 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5 * 2));
15579 DIP("%sh r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 2);
15585 /* ------------- LDRB Rd, [Rn, #imm5] ------------- */
15586 /* ------------- STRB Rd, [Rn, #imm5] ------------- */
15587 /* LDRB/STRB Rd, [Rn + imm5] */
15589 UInt rN = INSN0(5,3);
15597 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5));
15607 DIP("%sb r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5);
15638 /* ------------- LDMIA Rn!, {reglist} ------------- */
15640 UInt rN = INSN0(10,8);
15651 assign(oldRn, getIRegT(rN));
15664 /* Only do the writeback for rN if it isn't in the list of
15666 if (0 == (list & (1 << rN))) {
15667 putIRegT(rN,
15677 DIP("ldmia r%u!, {0x%04x}\n", rN, list);
15684 /* ------------- STMIA Rn!, {reglist} ------------- */
15686 UInt rN = INSN0(10,8);
15688 /* Empty lists aren't allowed. Also, if rN is in the list then
15691 if (valid && 0 != (list & (1 << rN))) {
15692 for (i = 0; i < rN; i++) {
15705 assign(oldRn, getIRegT(rN));
15715 putIRegT(rN,
15723 DIP("stmia r%u!, {0x%04x}\n", rN, list);
15921 UInt bW = INSN0(5,5); /* writeback Rn ? */
15923 UInt rN = INSN0(3,0);
15945 if (rN == 15) valid = False;
15948 if (bW == 1 && (regList & (1<<rN))) valid = False;
15952 if (rN == 15) valid = False;
15954 if (bW == 1 && (regList & (1<<rN))) valid = False;
15955 if (regList & (1<<rN)) {
15957 /* if Rn is in the list, then it must be the
15959 for (i = 0; i < rN; i++) {
15979 mk_ldm_stm(False/*!arm*/, rN, bINC, bBEFORE, bW, bL, regList);
15991 rN, bW ? "!" : "", regList);
15997 /* -------------- (T3) ADD{S}.W Rd, Rn, #constT -------------- */
16002 UInt rN = INSN0(3,0);
16004 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16006 if (!valid && rN == 13)
16013 assign(argL, getIRegT(rN));
16020 bS == 1 ? "s" : "", rD, rN, imm32);
16025 /* ---------------- (T4) ADDW Rd, Rn, #imm12 -------------- */
16029 UInt rN = INSN0(3,0);
16031 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16033 if (!valid && rN == 13)
16043 assign(argL, getIRegT(rN));
16047 DIP("addw r%u, r%u, #%u\n", rD, rN, imm12);
16052 /* ---------------- (T2) CMP.W Rn, #constT ---------------- */
16053 /* ---------------- (T2) CMN.W Rn, #constT ---------------- */
16059 UInt rN = INSN0(3,0);
16060 if (rN != 15) {
16065 assign(argL, getIRegT(rN));
16069 DIP("%s.w r%u, #%u\n", isCMN ? "cmn" : "cmp", rN, imm32);
16074 /* -------------- (T1) TST.W Rn, #constT -------------- */
16075 /* -------------- (T1) TEQ.W Rn, #constT -------------- */
16081 UInt rN = INSN0(3,0);
16082 if (!isBadRegT(rN)) { // yes, really, it's inconsistent with CMP.W
16091 assign(argL, getIRegT(rN));
16100 DIP("%s.w r%u, #%u\n", isTST ? "tst" : "teq", rN, imm32);
16105 /* -------------- (T3) SUB{S}.W Rd, Rn, #constT -------------- */
16106 /* -------------- (T3) RSB{S}.W Rd, Rn, #constT -------------- */
16113 UInt rN = INSN0(3,0);
16115 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16117 if (!valid && !isRSB && rN == 13 && rD == 13)
16124 assign(argL, getIRegT(rN));
16137 isRSB ? "rsb" : "sub", bS == 1 ? "s" : "", rD, rN, imm32);
16142 /* -------------- (T4) SUBW Rd, Rn, #imm12 ------------------- */
16146 UInt rN = INSN0(3,0);
16148 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
16149 if (!valid && rN == 13 && rD == 13)
16156 assign(argL, getIRegT(rN));
16160 DIP("subw r%u, r%u, #%u\n", rD, rN, imm12);
16170 UInt rN = 13; // SP
16179 assign(argL, getIRegT(rN));
16192 /* -------------- (T1) ADC{S}.W Rd, Rn, #constT -------------- */
16193 /* -------------- (T1) SBC{S}.W Rd, Rn, #constT -------------- */
16198 /* ADC: Rd = Rn + constT + oldC */
16199 /* SBC: Rd = Rn - constT - (oldC ^ 1) */
16201 UInt rN = INSN0(3,0);
16203 if (!isBadRegT(rN) && !isBadRegT(rD)) {
16209 assign(argL, getIRegT(rN));
16240 nm, bS == 1 ? "s" : "", rD, rN, imm32);
16245 /* -------------- (T1) ORR{S}.W Rd, Rn, #constT -------------- */
16246 /* -------------- (T1) AND{S}.W Rd, Rn, #constT -------------- */
16247 /* -------------- (T1) BIC{S}.W Rd, Rn, #constT -------------- */
16248 /* -------------- (T1) EOR{S}.W Rd, Rn, #constT -------------- */
16257 UInt rN = INSN0(3,0);
16259 if (!isBadRegT(rN) && !isBadRegT(rD)) {
16278 assign(argL, getIRegT(rN));
16293 nm, bS == 1 ? "s" : "", rD, rN, imm32);
16298 /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
16299 /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
16300 /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
16306 rN = INSN0(3,0);
16313 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
16316 && rN == 13 && imm5 == 0 && how == 0) {
16321 && rD == 13 && rN == 13 && imm5 == 0 && how == 0) {
16337 assign(argL, getIRegT(rN));
16370 nm, bS ? "s" : "", rD, rN, dis_buf);
16375 /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
16376 /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
16381 /* ADC: Rd = Rn + shifter_operand + oldC */
16382 /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
16383 UInt rN = INSN0(3,0);
16386 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
16392 assign(argL, getIRegT(rN));
16435 nm, bS ? "s" : "", rD, rN, dis_buf);
16440 /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
16441 /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
16442 /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
16443 /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
16444 /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */
16452 UInt rN = INSN0(3,0);
16455 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
16474 assign(rNt, getIRegT(rN));
16504 nm, bS ? "s" : "", rD, rN, dis_buf);
16509 /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
16510 /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
16511 /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
16512 /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
16517 UInt rN = INSN0(3,0);
16521 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
16531 assign(rNt, getIRegT(rN));
16535 rNt, how, rMt, rN, rM
16545 nm, bS ? "s" : "", rD, rN, rM);
16550 /* ------------ (T?) MOV{S}.W Rd, Rn, {shift} ------------ */
16551 /* ------------ (T?) MVN{S}.W Rd, Rn, {shift} ------------ */
16555 UInt rN = INSN1(3,0);
16556 if (!isBadRegT(rD) && !isBadRegT(rN)) {
16563 assign(rNt, getIRegT(rN));
16568 dis_buf, &oldRn, bS ? &oldC : NULL, rNt, how, imm5, rN
16587 /* -------------- (T?) TST.W Rn, Rm, {shift} -------------- */
16588 /* -------------- (T?) TEQ.W Rn, Rm, {shift} -------------- */
16594 UInt rN = INSN0(3,0);
16596 if (!isBadRegT(rN) && !isBadRegT(rM)) {
16603 assign(argL, getIRegT(rN));
16623 DIP("%s.w r%u, %s\n", isTST ? "tst" : "teq", rN, dis_buf);
16628 /* -------------- (T3) CMP.W Rn, Rm, {shift} -------------- */
16629 /* -------------- (T2) CMN.W Rn, Rm, {shift} -------------- */
16635 UInt rN = INSN0(3,0);
16637 if (!isBadRegT(rN) && !isBadRegT(rM)) {
16643 assign(argL, getIRegT(rN));
16656 DIP("%s.w r%u, %s\n", isCMN ? "cmn" : "cmp", rN, dis_buf);
16728 op Rt, [Rn, #-imm8] or
16729 op Rt, [Rn], #+/-imm8 or
16730 op Rt, [Rn, #+/-imm8]!
16763 UInt rN = INSN0(3,0);
16776 if (rN == 15)
16778 if (bW == 1 && rN == rT)
16802 assign(preAddr, getIRegT(rN));
16826 /* Update Rn if necessary. */
16828 vassert(rN != rT); // assured by validity check above
16829 putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
16885 /* Update Rn if necessary. */
16887 vassert(rN != rT); // assured by validity check above
16888 putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
16894 nm, rT, rN, bU ? '+' : '-', imm8);
16898 nm, rT, rN, bU ? '+' : '-', imm8);
16903 nm, rT, rN, bU ? '+' : '-', imm8);
16912 op Rt, [Rn, Rm, LSL #imm8]
16946 UInt rN = INSN0(3,0);
16955 if (rN == 15 || isBadRegT(rT) || isBadRegT(rM))
16959 if (rN == 15 || isBadRegT(rM))
16982 getIRegT(rN),
17042 nm, rT, rN, rM, imm2);
17050 op Rt, [Rn, +#imm12]
17083 UInt rN = INSN0(3,0);
17091 if (rN == 15 || isBadRegT(rT))
17096 if (rN == 15 || rT == 15)
17102 case, rN == 15 is allowable. In this case however, the
17103 value obtained for rN is (apparently)
17120 if (rN == 15) {
17122 assign(rNt, binop(Iop_And32, getIRegT(rN), mkU32(~3)));
17124 assign(rNt, getIRegT(rN));
17177 DIP("%s.w r%u, [r%u, +#%u]\n", nm, rT, rN, imm12);
17185 ldrd/strd Rt, Rt2, [Rn, #-imm8] or
17186 ldrd/strd Rt, Rt2, [Rn], #+/-imm8 or
17187 ldrd/strd Rt, Rt2, [Rn, #+/-imm8]!
17194 UInt rN = INSN0(3,0);
17201 if (bW == 1 && (rN == rT || rN == rT2)) valid = False;
17203 if (rN == 15) valid = False;
17213 assign(preAddr, getIRegT(rN));
17244 putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
17251 nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
17255 nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
17260 nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
17348 UInt rN = INSN0(3,0);
17351 if (bH/*ATC*/ || (rN != 13 && !isBadRegT(rM))) {
17360 getIRegT(rN),
17382 bH ? 'h' : 'b', rN, rM, bH ? ", LSL #1" : "");
17395 UInt rN = INSN0(3,0);
17400 if (!isBadRegT(rD) && !isBadRegT(rN) && msb <= 31) {
17409 assign(src, getIRegT(rN));
17420 isU ? "ubfx" : "sbfx", rD, rN, lsb, wm1 + 1);
17506 /* -------------- MUL.W Rd, Rn, Rm -------------- */
17509 UInt rN = INSN0(3,0);
17512 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17514 assign(res, binop(Iop_Mul32, getIRegT(rN), getIRegT(rM)));
17516 DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
17525 UInt rN = INSN0(3,0);
17530 && !isBadRegT(rN) && !isBadRegT(rM) && rDlo != rDhi) {
17533 getIRegT(rN), getIRegT(rM)));
17537 isU ? 'u' : 's', rDlo, rDhi, rN, rM);
17546 UInt rN = INSN0(3,0);
17550 if (!isBadRegT(rD) && !isBadRegT(rN)
17557 binop(Iop_Mul32, getIRegT(rN), getIRegT(rM))));
17560 isMLA ? "mla" : "mls", rD, rN, rM, rA);
17587 UInt rN = INSN0(3,0);
17591 if (!isBadRegT(rDlo) && !isBadRegT(rDhi) && !isBadRegT(rN)
17602 assign( argR, getIRegT(rN));
17612 isS ? 's' : 'u', rDlo, rDhi, rN, rM);
17638 UInt rN = INSN0(3,0);
17641 if (isBadRegT(rD) || rN == 13 || msb < lsb) {
17652 assign(src, rN == 15 ? mkU32(0) : getIRegT(rN));
17666 if (rN == 15) {
17671 rD, rN, lsb, msb-lsb+1);
17684 UInt rN = INSN0(3,0);
17688 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17693 assign(srcL, getIRegT(rN));
17701 isU ? 'u' : 's', rD, rN, rM, rot);
17713 UInt rN = INSN0(3,0);
17717 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17722 assign(srcL, getIRegT(rN));
17730 isU ? 'u' : 's', rD, rN, rM, rot);
17799 UInt rN = INSN0(3,0);
17802 if (!isBadRegT(rN) && (write_nzcvq || write_ge)) {
17804 assign(rNt, getIRegT(rN));
17807 write_nzcvq ? "f" : "", write_ge ? "g" : "", rN);
17826 UInt rN = INSN0(3,0);
17829 if (!isBadRegT(rT) && rN != 15) {
17837 binop(Iop_Add32, getIRegT(rN), mkU32(imm8 * 4)),
17840 DIP("ldrex r%u, [r%u, #+%u]\n", rT, rN, imm8 * 4);
17847 UInt rN = INSN0(3,0);
17851 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
17852 && rD != rN && rD != rT) {
17863 binop(Iop_Add32, getIRegT(rN), mkU32(imm8 * 4)),
17873 DIP("strex r%u, r%u, [r%u, #+%u]\n", rD, rT, rN, imm8 * 4);
