Lines Matching refs:fD
11284 // FTO{S,U}ID fD, dM
11290 UInt fD = (INSN(15,12) << 1) | bD;
11299 putFReg(fD, unop(Iop_ReinterpI32asF32,
11304 nCC(conq), fD, dM);
11307 putFReg(fD, unop(Iop_ReinterpI32asF32,
11312 nCC(conq), fD, dM);
11325 C4-98, C5-26 1 FSTMD cond 1100 1x00 Rn Fd 1010 offset
11326 C4-98, C5-28 2 FSTMDIA cond 1100 1x10 Rn Fd 1010 offset
11327 C4-98, C5-30 3 FSTMDDB cond 1101 0x10 Rn Fd 1010 offset
11329 C4-40, C5-26 1 FLDMD cond 1100 1x01 Rn Fd 1010 offset
11330 C4-40, C5-26 2 FLDMIAD cond 1100 1x11 Rn Fd 1010 offset
11331 C4-40, C5-26 3 FLDMDBD cond 1101 0x11 Rn Fd 1010 offset
11333 Regs transferred: F(Fd:D) .. F(Fd:d + offset)
11351 UInt fD = (INSN(15,12) << 1) | bD;
11376 if (fD + nRegs - 1 >= 32)
11423 putFReg(fD + i, loadLE(Ity_F32, addr), IRTemp_INVALID);
11425 storeLE(addr, getFReg(fD + i));
11442 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11445 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11448 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11498 UInt fD = (INSN(15,12) << 1) | bD;
11517 putFReg(fD, loadLE(Ity_F32,mkexpr(ea)), IRTemp_INVALID);
11519 storeLE(mkexpr(ea), getFReg(fD));
11522 bL ? "ld" : "st", nCC(conq), fD, rN,
11535 UInt fD = (INSN(15,12) << 1) | bD; /* dst/acc */
11545 putFReg(fD, triop(Iop_AddF32, rm,
11546 getFReg(fD),
11549 DIP("fmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11552 putFReg(fD, triop(Iop_AddF32, rm,
11553 getFReg(fD),
11558 DIP("fnmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11561 putFReg(fD, triop(Iop_AddF32, rm,
11562 unop(Iop_NegF32, getFReg(fD)),
11565 DIP("fmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11568 putFReg(fD, triop(Iop_AddF32, rm,
11569 unop(Iop_NegF32, getFReg(fD)),
11575 DIP("fnmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11578 putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
11580 DIP("fmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11583 putFReg(fD, unop(Iop_NegF32,
11587 DIP("fnmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11590 putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
11592 DIP("fadds%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11595 putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
11597 DIP("fsubs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11600 putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
11602 DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
11612 FCMPS cond 1110 1D11 0100 Fd 1010 01M0 Fm
11613 FCMPES cond 1110 1D11 0100 Fd 1010 11M0 Fm
11614 FCMPZS cond 1110 1D11 0101 Fd 1010 0100 0000
11615 FCMPZED cond 1110 1D11 0101 Fd 1010 1100 0000
11618 Z=0 Compare Fd:D vs Fm:M and set FPSCR 31:28 accordingly
11619 Z=1 Compare Fd:D vs zero
11633 UInt fD = (INSN(15,12) << 1) | bD;
11642 assign(argL, unop(Iop_F32toF64, getFReg(fD)));
11676 DIP("fcmpz%ss%s s%u\n", bN ? "e" : "", nCC(conq), fD);
11679 nCC(conq), fD, fM);
11693 UInt fD = (INSN(15,12) << 1) | bD;
11699 putFReg(fD, getFReg(fM), condT);
11700 DIP("fcpys%s s%u, s%u\n", nCC(conq), fD, fM);
11705 putFReg(fD, unop(Iop_AbsF32, getFReg(fM)), condT);
11706 DIP("fabss%s s%u, s%u\n", nCC(conq), fD, fM);
11711 putFReg(fD, unop(Iop_NegF32, getFReg(fM)), condT);
11712 DIP("fnegs%s s%u, s%u\n", nCC(conq), fD, fM);
11718 putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
11719 DIP("fsqrts%s s%u, s%u\n", nCC(conq), fD, fM);
11730 // F{S,U}ITOS fD, fM
11743 UInt fD = (INSN(15,12) << 1) | bD;
11749 putFReg(fD, binop(Iop_F64toF32,
11754 DIP("fsitos%s s%u, s%u\n", nCC(conq), fD, fM);
11757 putFReg(fD, binop(Iop_F64toF32,
11762 DIP("fuitos%s s%u, s%u\n", nCC(conq), fD, fM);
11767 // FTO{S,U}IS fD, fM
11774 UInt fD = (INSN(15,12) << 1) | bD;
11783 putFReg(fD, unop(Iop_ReinterpI32asF32,
11788 nCC(conq), fD, fM);
11792 putFReg(fD, unop(Iop_ReinterpI32asF32,
11797 nCC(conq), fD, fM);
11823 UInt fD = (INSN(15,12) << 1) | bD;
11827 putFReg(fD, binop(Iop_F64toF32, mkexpr(rmode), getDReg(dM)),
11829 DIP("fcvtsd%s s%u, d%u\n", nCC(conq), fD, dM);
