Lines Matching refs:TO
24 along with this program; if not, write to the Free Software
32 used to endorse or promote products derived from this software
63 to zero, whereas we keep maximum accuracy. However, using
70 way to express that right now. Ah well.
93 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11
99 fragments designed for Valgrind to catch.
103 /* Translates PPC32/64 code to IR. */
143 down in disInstr_PPC, so that we don't have to pass them around
147 /* We need to know this to do sub-register accesses correctly. */
150 /* Pointer to the guest code area. */
153 /* The guest address corresponding to guest_code[0]. */
163 /* Is our guest binary 32 or 64bit? Set at each call to
167 // Given a pointer to a function as obtained by "& functionname" in C,
168 // produce a pointer to the actual entry point for the function. For
175 /* f is a pointer to a 3-word function descriptor, of which the
315 PPC_GST_TISTART,// For icbi: start of area to invalidate
316 PPC_GST_TILEN, // For icbi: length of area to invalidate
331 /* Produce the 32-bit pattern corresponding to the supplied
350 begin->end works from right to left, 0=lsb
388 /* Add a statement to the list held by "irsb". */
531 /* expand V128_8Ux16 to 2x V128_16Ux8's */
549 /* expand V128_8Sx16 to 2x V128_16Sx8's */
567 /* expand V128_16Uto8 to 2x V128_32Ux4's */
585 /* expand V128_16Sto8 to 2x V128_32Sx4's */
603 /* break V128 to 4xI32's, then sign-extend to I64's */
630 /* break V128 to 4xI32's, then zero-extend to I64's */
657 /* Signed saturating narrow 64S to 32 */
680 /* Unsigned saturating narrow 64S to 32 */
700 /* Signed saturate narrow 64->32, combining to V128 */
717 /* Unsigned saturate narrow 64->32, combining to V128 */
925 /* Ditto, but write to a reg instead. */
983 /* Ditto, but write to a reg instead. */
1040 /* Ditto, but write to a reg instead. */
1177 /* Exit the trace if ADDR (intended to be a guest memory address) is
1213 the address of the next instruction to be executed.
1259 Indexing from BI to guest state:
1303 to be zero. */
1324 /* Dually, write the least significant bit of BIT to the specified CR
1358 whichever bit it is, all other bits are guaranteed to be zero. In
1770 /* Incoming oldca is assumed to hold the values 0 or 1 only. This
1819 /* The shift amount is guaranteed to be in 0 .. 63 inclusive.
1848 0. Since the shift amount is known to be in the range
1888 /* Incoming oldca is assumed to hold the values 0 or 1 only. This
1938 /* The shift amount is guaranteed to be in 0 .. 31 inclusive.
1968 Since the shift amount is known to be in the range 0 .. 31
1992 /* The shift amount is guaranteed to be in 0 .. 63 inclusive.
2023 Since the shift amount is known to be in the range 0 .. 63
2066 /*--- Read/write to guest-state --- */
2141 /* Vex-generated code expects the FPSCR to be set as follows:
2142 all exceptions masked, round-to-nearest.
2143 This corresponds to a FPSCR value of 0x0. */
2169 guaranteed to be zero. */
2261 /* Write masked src to the given reg */
2270 /* Allow writes to Rounding Mode */
2290 /* Give EmWarn for attempted writes to:
2298 side-exit to the next insn, reporting the warning,
2318 /* Write the least significant nibble of src to the specified
2398 do_rc = True; // Always record to CR
2452 do_rc = True; // All below record to CR
2502 case 0x0EA: { // addme (Add to Minus One Extended, PPC32 p354)
2529 case 0x0CA: { // addze (Add to Zero Extended, PPC32 p355)
2563 /* rD[hi32] are undefined: setting them to sign of lo32
2622 /* rD[hi32] are undefined: setting them to sign of lo32
2644 /* rD[hi32] are undefined: setting them to sign of lo32
2663 /* rD[hi32] are undefined: setting them to sign of lo32
2962 remove the false dependency, which has been known to cause
2963 memcheck to produce false errors. */
2981 remove the false dependency, which has been known to cause
2982 memcheck to produce false errors. */
3040 do_rc = True; // Always record to CR
3048 do_rc = True; // Always record to CR
3078 do_rc = True; // All below record to CR
3241 case 0x2DF: { // mftgpr (move floating-point to general purpose register)
4187 /* when crossing into a new dest register, set it to zero. */
4282 registers to be loaded. It should. */
4303 registers to be loaded. It should. Although considering
4304 that that can only be detected at run time, it's not easy to
4410 /* We have to invert the sense of the information held in
4411 cr_bi. For that we need to know which bit
4450 /* Hack to pass through code that just wants to read the PC */
4508 way to compute it. Anding them together gives a value which
4536 b11to15 are a branch hint, and so we only need to ensure it's
4544 case 0x210: // bcctr (Branch Cond. to Count Register, PPC32 p363)
4574 case 0x010: { // bclr (Branch Cond. to Link Register, PPC32 p365)
4607 "branch-to-lr (unconditional return)" );
4611 return address of its caller to the insn following this
4733 static Bool do_trap ( UChar TO,
4764 if ((TO & b11100) == b11100 || (TO & b00111) == b00111) {
4790 if (TO & 16) { // L <s R
4794 if (TO & 8) { // L >s R
4798 if (TO & 4) { // L == R
4802 if (TO & 2) { // L <u R
4806 if (TO & 1) { // L >u R
4823 UChar TO = ifieldRegDS(theInstr);
4833 uncond = do_trap( TO,
4838 if (TO == 4) {
4841 DIP("tw%di r%u,%d\n", (Int)TO, (UInt)rA_addr, (Int)simm16);
4847 uncond = do_trap( TO, getIReg(rA_addr), mkU64( (ULong)simm16 ), cia );
4848 if (TO == 4) {
4851 DIP("td%di r%u,%d\n", (Int)TO, (UInt)rA_addr, (Int)simm16);
4874 UChar TO = ifieldRegDS(theInstr);
4886 uncond = do_trap( TO,
4892 if (TO == 4) {
4895 DIP("tw%d r%u,r%u\n", (Int)TO, (UInt)rA_addr, (UInt)rB_addr);
4901 uncond = do_trap( TO, getIReg(rA_addr), getIReg(rB_addr), cia );
4902 if (TO == 4) {
4905 DIP("td%d r%u,r%u\n", (Int)TO, (UInt)rA_addr, (UInt)rB_addr);
4941 Valgrind can back the guest up to this instruction if it needs
4942 to restart the syscall. */
4945 /* It's important that all ArchRegs carry their up-to-date value
4947 forces any TempRegs caching ArchRegs to be flushed. */
4963 once to run. In effect, a thread can make a reservation, but we don't
4965 the scheduler switches to another thread (run_thread_for_a_while()).
5010 /* Insert a memory fence, just to be on the safe side. */
5016 /* According to the PowerPC ISA version 2.05, b0 (called EH
5017 in the documentation) is merely a hint bit to the
5018 hardware, I think as to whether or not contention is
5035 // Note this has to handle stwcx. in both 32- and 64-bit modes,
5048 // Get the data to be stored, and narrow to 32 bits if necessary
5076 the programmer to specify a less expensive operation on
5100 are carried through to the generated code. */
5107 /* According to the PowerPC ISA version 2.05, b0 (called EH
5108 in the documentation) is merely a hint bit to the
5109 hardware, I think as to whether or not contention is
5141 // Get the data to be stored
5416 /* Generates code to swap the byte order in an Ity_I32. */
5434 /* Generates code to swap the byte order in the lower half of an Ity_I32,
5550 case 0x200: { // mcrxr (Move to Cond Register from XER, PPC32 p466)
5556 /* Move XER[0-3] (the top 4 bits of XER) to CR[crfD] */
5697 // b20==0: mtcrf (Move to Cond Register Fields, PPC32 p477)
5698 // b20==1: mtocrf (Move to One Cond Reg Field)
5705 1 field is written. It seems more robust to decline to
5717 /* Write to each field specified by CRM */
5730 case 0x1D3: // mtspr (Move to Special-Purpose Register, PPC32 p483)
5786 seems to generate values of 8 and 10 for b21to25. */
5839 case 0x3F6: { // dcbz (Data Cache Block Clear to Zero, PPC32 p387)
5840 // dcbzl (Data Cache Block Clear to Zero Long, bug#135264)
5859 /* Round EA down to the start of the containing block. */
5869 /* Round EA down to the start of the containing block. */
5891 /* Round EA down to the start of the containing block. */
5921 IRRoundingMode. PPCRoundingMode encoding is different to
5922 IRRoundingMode, so need to map it.
5929 to nearest | 00 | 00
5930 to zero | 01 | 11
5931 to +infinity | 10 | 10
5932 to -infinity | 11 | 01
6104 the values are truncated and denormalised (not rounded) to turn
6112 /* Use Iop_TruncF64asF32 to truncate and possible denormalise
6113 the value to be stored in the correct way, without any
6233 operation. In reality we should set cr1 to indicate the
6235 simulating exceptions, the exception status will appear to be
6280 // to fsqrt (double-precision). So use SqrtF64, not SqrtF64r32.
6473 operation. In reality we should set cr1 to indicate the
6475 simulating exceptions, the exception status will appear to be
6479 /* Bind the rounding mode expression to a temp; there's no
6481 to use it twice. */
6489 /* The rounding in this is all a bit dodgy. The idea is to only do
6626 /* Map compare result from IR to PPC32 */
6671 /* CAB: TODO?: Support writing cc to FPSCR->FPCC ?
6719 operation. In reality we should set cr1 to indicate the
6721 simulating exceptions, the exception status will appear to be
6733 case 0x00C: // frsp (Float Round to Single, PPC32 p423)
6738 case 0x00E: // fctiw (Float Conv to Int, PPC32 p404)
6748 case 0x00F: // fctiwz (Float Conv to Int, Round to Zero, PPC32 p405)
6758 case 0x32E: // fctid (Float Conv to Int DWord, PPC64 p437)
6767 case 0x32F: // fctidz (Float Conv to Int DWord, Round to Zero, PPC64 p437)
6785 case 0x188: // frin (Floating Round to Integer Nearest)
6790 case 0x1A8: // friz (Floating Round to Integer Toward Zero)
6795 case 0x1C8: // frip (Floating Round to Integer Plus)
6800 case 0x1E8: // frim (Floating Round to Integer Minus)
6809 /* need to preserve sign of zero */
7048 case 0x026: { // mtfsb1 (Move to FPSCR Bit 1, PPC32 p479)
7062 case 0x040: { // mcrfs (Move to Condition Register from FPSCR, PPC32 p465)
7084 case 0x046: { // mtfsb0 (Move to FPSCR Bit 0, PPC32 p478)
7098 case 0x086: { // mtfsfi (Move to FPSCR Field Immediate, PPC32 p481)
7129 case 0x2C7: { // mtfsf (Move to FPSCR Fields, PPC32 p480)
7255 case 0x644: { // mtvscr (Move to VSCR, AV p130)
7805 /* break V128 to 4xI32's, zero-extending to I64's */
7830 /* saturate-narrow to 32bit, and combine to V128 */
7845 /* break V128 to 4xI32's, sign-extending to I64's */
7870 /* saturate-narrow to 32bit, and combine to V128 */
7881 /* break V128 to 4xI32's, sign-extending to I64's */
7896 /* saturate-narrow to 32bit, and combine to V128 */
7904 /* break V128 to 4xI32's, sign-extending to I64's */
7914 /* saturate-narrow to 32bit, and combine to V128 */
7922 /* break V128 to 4xI32's, sign-extending to I64's */
7932 /* saturate-narrow to 32bit, and combine to V128 */
8026 case 0x006: // vcmpequb (Compare Equal-to Unsigned B, AV p160)
8032 case 0x046: // vcmpequh (Compare Equal-to Unsigned HW, AV p161)
8038 case 0x086: // vcmpequw (Compare Equal-to Unsigned W, AV p162)
8257 (separating out adjacent lanes to different vectors) */
8292 /* break V128 to 4xI32's, zero-extending to I64's */
8307 /* saturate-narrow to 32bit, and combine to V128 */
8330 /* break V128 to 4xI32's, sign-extending to I64's */
8345 /* saturate-narrow to 32bit, and combine to V128 */
8534 /* limited to two args for IR, so have to play games... */
8541 /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
8542 IR specifies, and also to hide irrelevant bits from
8781 /* Using shifts to compact pixel elements, then packing them */
8866 /* Using shifts to isolate pixel elements, then expanding them */
8899 /* identical to
9031 case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173)
9075 case 0x0C6: // vcmpeqfp (Compare Equal-to FP, AV p159)
9081 case 0x1C6: // vcmpgefp (Compare Greater-than-or-Equal-to, AV p163)
9106 Perhaps better to have an irop Iop_isNan32Fx4, but then we'd
9117 // finally, just shift gt,lt to correct position
9161 /* scale = 2^UIMM, cast to float, reinterpreted as uint */
9189 case 0x38A: // vctuxs (Convert to Unsigned Fixed-Point W Saturate, AV p172)
9196 case 0x3CA: // vctsxs (Convert to Signed Fixed-Point W Saturate, AV p171)
9213 case 0x20A: // vrfin (Round to FP Integer Nearest, AV p231)
9218 case 0x24A: // vrfiz (Round to FP Integer toward zero, AV p233)
9223 case 0x28A: // vrfip (Round to FP Integer toward +inf, AV p232)
9228 case 0x2CA: // vrfim (Round to FP Integer toward -inf, AV p230)
9304 /* We may be asked to update the guest CIA before going further. */
9352 /* branch-and-link-to-noredir %R11 */
9353 DIP("branch-and-link-to-noredir r11\n");
9573 /* A hack to check for P6 capability . . . */
10020 vex_printf("disInstr(ppc): declined to decode an FP insn.\n");
10024 vex_printf("disInstr(ppc): declined to decode an AltiVec insn.\n");
10029 "declined to decode a GeneralPurpose-Optional insn.\n");
10034 "declined to decode a Graphics-Optional insn.\n");
10046 not been executed, and (is currently) the next to be executed.
10047 CIA should be up-to-date since it made so at the start of each
10144 // /* Welcome ... to SSA R Us. */
10178 // (to count the 1s, which is the number of leading zeroes, or 32
