Lines Matching full:rounding
52 * FP rounding mode observed only for float->int conversions
54 for float-to-float rounding. For all other operations,
3464 /* --------- Get/put the FPU rounding mode. --------- */
3476 /* --------- Synthesise a 2-bit FPU rounding mode. --------- */
3972 rounding mode. Therefore, pass the 16-bit value
7351 /* Get the current SSE rounding mode. */
8390 I32 in mmx, according to prevailing SSE rounding mode */
8392 I32 in mmx, rounding towards zero */
8445 I32 in ireg, according to prevailing SSE rounding mode */
8447 I32 in ireg, rounding towards zero */
8514 /* The only thing we observe in %mxcsr is the rounding mode.
8838 /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
8847 /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
9486 I32 in mmx, according to prevailing SSE rounding mode */
9488 I32 in mmx, rounding towards zero */
9693 I32 in ireg, according to prevailing SSE rounding mode */
9695 I32 in ireg, rounding towards zero */
9732 low 1/4 xmm(G), according to prevailing SSE rounding mode */
9815 lo half xmm(G), and zero upper half, rounding towards zero */
9858 xmm(G), rounding towards zero */
12601 the rounding mode is specified directly by the immediate byte.)
12637 /* (imm & 3) contains an Intel-encoded rounding mode. Because
12639 we can use that value directly in the IR as a rounding
