Lines Matching defs:code
52 /* Vex-generated code expects to run with the FPU set as follows: all
57 fpscr should therefore be zero on entry to Vex-generated code, and
90 - The code array, that is, the insns selected so far.
109 HInstrArray* code;
135 addHInstr(env->code, instr);
391 Generating code which is both efficient and correct when
406 regs. This always gives correct code, but it also gives a bunch
468 code to get the arg values into the argument rregs. If we run
575 /* None of these insns, including any spill code that might
617 code list. Return a reg holding the result. This reg will be a
633 expression, possibly also adding insns to the code list as a
702 expression, possibly also adding insns to the code list as a
768 expression, possibly also adding insns to the code list as a
947 /* Generate code to evaluated a bit-typed expression, returning the
948 condition code which would correspond when the expression would
974 /* Generate code for the arg, and negate the test condition */
1785 by subsequent code emitted by the caller. */
5250 code emitted by the caller. */
5297 // In which case we'll have to generate more longwinded code.
5420 code emitted by the caller. */
5455 // In which case we'll have to generate more longwinded code.
5668 // In which case we'll have to generate more longwinded code.
5676 // In which case we'll have to generate more longwinded code.
5909 /* Doesn't generate any executable code ... */
5962 /* Translate an entire SB to arm code. */
5985 /* Set up output code array. */
5986 env->code = newHInstrArray();
6041 env->code->n_vregs = env->vreg_ctr;
6043 return env->code;
