Lines Matching defs:code
61 GPR12 if mode64: not used - exceptions / global linkage code
106 Vex-generated code expects to run with the FPU set as follows: all
230 - The code array, that is, the insns selected so far.
260 HInstrArray* code;
296 addHInstr(env->code, instr);
381 using this amode. That is so that, for 64-bit code generation, any
387 ignored for 32-bit code generation. */
652 Generating code which is both efficient and correct when
667 regs. This always gives correct code, but it also gives a bunch
741 code to get the arg values into the argument rregs. */
843 /* None of these insns, including any spill code that might
1009 Generates code for AvSplat
1125 code list. Return a reg holding the result. This reg will be a
1840 /* I believe this generates correct code for both 32- and
1975 expression, possibly also adding insns to the code list as a
2308 /* Generate code to evaluated a bit-typed expression, returning the
2309 condition code which would correspond when the expression would
2336 /* Generate code for the arg, and negate the test condition */
2483 case they must not be changed by subsequent code emitted by the
2568 case they must not be changed by subsequent code emitted by the
2992 We generate pretty poor code here (should be ok both for
2994 part the latter optimisation will apply and hence this code
3025 code emitted by the caller. */
4049 /* Doesn't generate any executable code ... */
4114 /* Translate an entire BS to ppc code. */
4150 /* Set up output code array. */
4151 env->code = newHInstrArray();
4212 env->code->n_vregs = env->vreg_ctr;
4213 return env->code;
